Method of operation for a configurable number theoretic transform (NTT) butterfly circuit for homomorphic encryption

1. A circuit, comprising:

number theoretic transform (NTT) circuitry including selection circuitry to configure the NTT circuitry into one of a first mode of operation or a second mode of operation;

wherein for the first mode of operation,

the selection circuitry is responsive to a first control signal to configure the NTT circuitry into a first logic processing unit; and

wherein for the second mode of operation,

the selection circuitry is responsive to a second control signal to configure the NTT circuitry into a second logic processing unit that is different than the first logic processing unit.

2. The circuit of claim 1 , wherein:

for the first mode of operation, the first logic processing unit carries out a ciphertext (C txt ) addition function; and

for the second mode of operation, the second processing unit carries out a C txt multiplication function.

3. The circuit of claim 1 , wherein the NTT circuitry further includes a high input word path and a low input word path, wherein:

the high input word path includes

a first adder/subtractor,

a first multiplier, and

wherein the selection circuitry is coupled to the first adder/subtractor and the first multiplier and including respective first bypass paths to selectively bypass the first adder/subtractor and the first multiplier; and

the low input word path includes

a second adder/subtractor,

a second multiplier, and

wherein the selection circuitry is coupled to the second adder/subtractor and the second multiplier and including respective second bypass paths to selectively bypass the second adder/subtractor and the second multiplier.

4. The circuit of claim 3 , wherein:

the high and low input word paths are selectively cross-coupled.

5. The circuit of claim 3 , wherein the first adder/subtractor and the second adder/subtractor each comprises:

a regular add/subtract unit having an output fed to a modular reduction unit.

6. The circuit of claim 5 , wherein the regular add/subtract unit comprises a parallel adder.

7. The circuit of claim 5 , wherein the modular reduction unit comprises one from the group including:

a Barrett modular reduction unit, a special prime modular reduction unit, and a Montgomery modular multiplication unit.

8. The circuit of claim 3 , wherein the first multiplier and the second multiplier each comprise:

a modular adder.

9. The circuit of claim 3 , wherein the first multiplier and the second multiplier each comprise:

an integer multiplier having an output fed to a modular reduction unit.

10. The circuit of claim 9 , wherein the integer multiplier comprises:

a parallel integer multiplier.

11. A circuit, comprising:

number theoretic transform (NTT) circuitry including

selection circuitry responsive to a first control signal value to configure the NTT circuitry into a first mode of operation; and

wherein the selection circuitry is responsive to a second control signal value that is different than the first control signal value to configure the NTT circuitry into a second mode of operation that is different than the first mode of operation.

12. The circuit of claim 11 , wherein:

for the first mode of operation, the NTT circuitry is configured into a first logic processing unit; and

for the second mode of operation, the NTT circuitry is configured into a second logic processing unit that is different from the first logic processing unit.

13. The circuit of claim 12 , wherein:

for the first mode of operation, the first logic processing unit carries out a ciphertext (C txt ) addition function; and

for the second mode of operation, the second processing unit carries out a C txt multiplication function.

14. The circuit of claim 11 , wherein the NTT circuitry includes:

a high input word path;

a low input word path; and

wherein the selection circuitry includes bypass circuitry to bypass portions of the high input word path or the low input word path based on receipt of the first control signal value or the second control signal value.

15. The circuit of claim 14 , wherein:

the high and low input word paths are selectively cross-coupled.

16. The circuit of claim 14 , wherein:

the high input word path includes

a first adder/subtractor,

a first multiplier, and

 wherein the selection circuitry is coupled to the first adder/subtractor and the first multiplier and wherein the bypass circuitry is to selectively bypass the first adder/subtractor and the first multiplier; and

the low input word path includes

a second adder/subtractor,

a second multiplier, and

 wherein the selection circuitry is coupled to the second adder/subtractor and the second multiplier and wherein the bypass circuitry is to selectively bypass the second adder/subtractor and the second multiplier.

17. A method of operation in a homomorphic processor integrated circuit (IC) chip, the method comprising:

configuring, with a selection circuit responsive to a first control signal value, a Number Theoretic Transform (NTT) circuit for a first mode of operation; and

configuring, with the selection circuit responsive to a second control signal value that is different than the first control signal value, the NTT circuit for a second mode of operation that is different than the first mode of operation.

18. The method according to claim 17 , wherein:

for the first mode of operation, the configuring configures the NTT circuitry into a first logic processing unit; and

for the second mode of operation, the configuring configures the NTT circuitry into a second logic processing unit that is different from the first logic processing unit.

19. The method of claim 18 , wherein:

performing, in the first mode of operation, a ciphertext (C txt ) addition function with the first logic processing unit; and

performing, in the second mode of operation, a C txt multiplication function with the second processing unit.