IP Library › Granted Patent US 12,342,449
Granted Patent B2
US 12,342,449 · App. 17/953,744 · Granted Jun 24, 2025

Multilayered nonpolar, chromium, copper material coatings of power electronics boards for thermal management

Inventors: Tarek Gebrael (Champaign, IL); Arielle R. Gamboa (Urbana, IL); Jiaqi Li (Urbana, IL); Nenad Miljkovic (Urbana, IL); Shayan Aflatounian (Urbana, IL)
Assignee: The Board of Trustees of the University of Illinois
H05K1/0209C23C14/042C23C14/205C23C14/24C23C14/34C23C18/1605C23C18/38C23C28/023C25D3/38C25D7/00H05K3/22
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Quick Facts
Patent No.
US 12,342,449
App. No.
17/953,744
Granted
Jun 24, 2025
Kind
B2
Abstract

An apparatus includes a printed circuit board (PCB), a power component disposed on the PCB, the power component to generate heat, and a multilayered coating disposed over the power component and at least a portion of the PCB to dissipate heat from the power component, the multilayered including: an electrical insulation layer comprising a non-polar compound and disposed on the power component and the at least a portion of the PCB; a chromium layer disposed on the electrical insulation layer; and a copper layer disposed on the chromium layer that is at least 10 microns (μm) thick, the copper layer conformally adhered to a top of the power component and to the PCB.

Claims (62)

1. An apparatus comprising:

a printed circuit board (PCB);

a power component disposed on the PCB, the power component to generate heat; and

a multilayered coating disposed over the power component and at least a portion of the PCB to dissipate the heat from the power component, the multilayered coating comprising:

an electrical insulation layer comprising a non-polar compound and disposed on the power component and the at least a portion of the PCB;

a chromium layer disposed on the electrical insulation layer; and

a copper layer disposed on the chromium layer that is at least 10 microns (μm) thick, the copper layer conformally adhered to a top of the power component and to the PCB.

2. The apparatus of claim 1 , wherein the electrical insulation layer is from 7 to 11 microns (μm) thick.

3. The apparatus of claim 1 , wherein the chromium layer is from 10 to 30 nanometer (nm) thick.

4. The apparatus of claim 1 , wherein the copper layer comprises multiple copper sublayers comprising:

a thermally-evaporated copper layer that is from 40 to 60 nm thick disposed on the chromium layer;

an electroless-deposited copper layer that is from 0.15 to 0.35 μm thick disposed on the thermally-evaporated copper layer; and

an electroplated copper layer disposed on the electroless-deposited copper layer.

5. The apparatus of claim 1 , further comprising an electronic device disposed on the PCB that has a temperature limit lower a temperature limit of the power component, wherein the copper layer comprises a heat shield region over the electronic device, the heat shield region being sized to reduce a temperature of the electronic device to a target temperature.

6. The apparatus of claim 1 , further comprising:

an electronic device that is to be heated by the power component disposed on the PCB a distance away from the power component, wherein the multilayered coating covers an area of the PCB adjacent to the power component and a thermal routed path of the PCB between the power component and the electronic device; and

a thermal insulation layer disposed on the multilayered coating.

7. The apparatus of claim 6 , wherein the electronic device is a battery or a storage cell and the distance away comprises at least 20 millimeters.

8. The apparatus of claim 1 , wherein the electrical insulation layer is a non-polar dielectric, Parylene C, Parylene HT, or Parylene N.

9. The apparatus of claim 1 , wherein at least a portion of the copper layer comprises fins or grooves that increase a surface area of the copper layer.

10. A method comprising:

coating a power component and at least a portion of a printed circuit board (PCB) on which the power component is disposed with an electrical insulation layer comprising a non-polar compound;

depositing, using one of thermal evaporation or sputtering, a chromium layer on the electrical insulation layer;

depositing, using one of thermal evaporation or sputtering, a first copper layer on the chromium layer;

depositing, using electroless deposition, a second copper layer on the first copper layer; and

depositing, using copper electroplating, a third copper layer on the second copper layer.

11. The method of claim 10 , further comprising, before the coating, covering select components disposed on, and select areas of, the at least a portion of the PCB with a polyimide adhesive tape to protect the select components and select areas that are to be accessed during later PCB operations.

12. The method of claim 10 , further comprising, after the coating, covering a region of the at least a portion of the PCB with a mask that is not to be layered with the chromium and copper layers.

13. The method of claim 12 , wherein the mask defines a thermal routed path between the power component and an electronic device that is disposed on the at least a portion of the PCB a distance away from the power component, wherein the electronic device is to be heated by the power component, and the method further comprising, after deposition of the first and second copper layers, depositing a thermal insulation layer on the copper layers that are defined by the mask.

14. The method of claim 10 , further comprising, before the coating:

applying an adhesion promoter for the electrical insulation layer, the adhesion promoter comprising gamma-methacryloxypropyltrimethoxysilane (γ-MPS); and

wherein the coating of the power component and the at least a portion of the PCB with the electrical insulation layer is done within 30 hours of applying the adhesion promoter.

15. The method of claim 10 , wherein:

the chromium layer is deposited until the chromium layer is 0 to 30 nanometer (nm) thick;

the first copper layer is deposited until the first copper layer is 40 to 60 nm thick; and

the second copper layer is deposited until the second copper layer is 0.15 to 0.35 μm thick.

16. The method of claim 10 , wherein depositing the second copper layer comprises:

immersing the PCB into an acidic stannous chloride solution for between 40 to 60 seconds at room temperature;

rinsing the PCB thoroughly in deionized water;

without waiting to dry, immersing the PCB into an acidic palladium chloride solution for 40 to 60 seconds at room temperature;

rinsing the PCB thoroughly in the deionized water;

without allowing to dry, immersing the PCB in an electroless copper solution for an excess of two minutes at one of room temperature or 40° Celsius;

rinsing the PCB in the deionized water; and

drying the PCB with nitrogen.

17. The method of claim 16 , wherein the excess of two minutes comprises at least three minutes.

18. The method of claim 10 , wherein the copper electroplating is performed using a current density of 75 amperes per meter squared or less to prevent fragile porous copper deposition.

19. The method of claim 10 , further comprising employing a mask to form a heat shield region in the chromium layer and the first copper layer, wherein the second copper layer and the third copper layer are not deposited on the heat shield region, which defines a shielded area over an electronic device disposed on the PCB that has a temperature limit lower than a temperature limit of the power component, the heat shield region being sized to reduce a temperature of the electronic device to a target temperature.

20. The method of claim 10 , wherein the electrical insulation layer is a non-polar dielectric, Parylene C, Parylene HT, or Parylene N.

21. The method of claim 10 , wherein before the depositing, using the copper electroplating, applying a mask over the second copper layer, the mask to create fins or grooves in the third copper layer.

22. A device comprising:

a printed circuit board (PCB);

a power source;

power electronics disposed on the PCB that is to generate heat when powered by the power source; and

a multilayered coating disposed over the power electronics and at least a portion of the PCB to dissipate the heat from the power electronics, the multilayered coating comprising:

an electrical insulation layer comprising a non-polar compound and disposed on the power electronics and the at least a portion of the PCB;

a chromium layer disposed on the electrical insulation layer;

a thermally-evaporated copper layer deposited on the chromium layer;

an electroless-deposited copper layer deposited on the thermally-evaporated copper layer; and

an electroplated copper layer deposited on the electroless-deposited copper layer.

23. The device of claim 22 , wherein the electroless-deposited copper layer and the electroplated copper layer are conformally adhered to the power electronics and the at least a portion of the PCB, and wherein the copper layers combined are from 10 μm to 600 μm thick.

24. The device of claim 22 , wherein the electrical insulation layer is a non-polar dielectric, Parylene C, Parylene HT, or Parylene N.

25. The device of claim 22 , wherein the electroplated copper layer comprises fins or grooves to increase a surface area of the electroplated copper layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2022
From: GEBRAEL, TAREK; GAMBOA, ARIELLE R.; LI, JIAQI; MILJKOVIC, NENAD; AFLATOUNIAN, SHAYAN
To: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
Reel/Frame 061992/0657 →
Continuity (2)
Provisional Application 63249287 · Sep 28, 2021
Related Publication 20230103241A1 · Mar 30, 2023
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