Energy efficient tag partitioning in cache memory

1. A method, comprising:

receiving a memory address at an m-way set-associative cache, wherein the memory address is partitioned into a tag, an index, and an offset, wherein the m-way set-associative cache stores a set of cache entries, and wherein the m-way set-associative cache includes a first structure to store a first subset of tag bits corresponding to the set of cache entries and a second structure to store a second subset of tag bits corresponding to the set of cache entries;

using the index to select m entries in the first structure;

matching a first portion of tag bits of the memory address with the m entries in the first structure; and

in response to the first portion of tag bits of the memory address matching n entries in the first structure, where n is less than m, matching a second portion of tag bits of the memory address with n entries in the second structure corresponding to the n entries in the first structure; and

wherein the matching the first portion of tag bits of the memory address with the m entries in the first structure and the matching the second portion of tag bits of the memory address with n entries in the second structure is performed in a single clock cycle.

2. The method of claim 1 , further comprising:

in response to the first portion of tag bits of the memory address not matching any entry in the m entries, determining a cache miss; and

in response to the second portion of tag bits of the memory address not matching any entry in the n entries in the second structure, determining a cache miss.

3. The method of claim 2 , further comprising:

in response to the second portion of tag bits of the memory address matching an entry in the n entries in the second structure, determining a cache hit.

4. The method of claim 3 , further comprising:

in response to determining a cache hit, using the offset to retrieve a word from a cache entry corresponding to the matching entry in the n entries in the second structure.

5. The method of claim 1 , wherein the matching the first portion of tag bits of the memory address with the m entries in the first structure comprises matching each bit of the first portion of tag bits with a corresponding bit of each entry in the m entries in the first structure.

6. The method of claim 1 , further comprising:

receiving a memory block, wherein the memory block corresponds to a first tag and a first index;

storing a first subset of tag bits of the first tag in the first structure based on the first index; and

storing a second subset of tag bits of the first tag in the second structure based on the first index.

7. The method of claim 6 , further comprising:

storing the memory block in the m-way set-associative cache.

8. An integrated circuit (IC), comprising:

a first circuit to store a set of cache entries, wherein each cache entry includes one or more words of data, wherein each word of data corresponds to a memory address, and wherein the memory address is partitioned into a tag, an index, and an offset;

a first structure to store a first subset of tag bits corresponding to the set of cache entries;

a second structure to store a second subset of tag bits corresponding to the set of cache entries; and

a second circuit to:

use the index to select m entries in the first structure;

match a first portion of tag bits of the memory address with the m entries in the first structure;

in response to the first portion of tag bits of the memory address matching n entries in the first structure, where n is less than m, match a second portion of tag bits of the memory address with n entries in the second structure corresponding to the n entries in the first structure; and

wherein the matching the first portion of tag bits of the memory address with the m entries in the first structure and the matching the second portion of tag bits of the memory address with n entries in the second structure is performed in a single clock cycle.

9. The IC of claim 8 , wherein the second circuit to:

in response to the first portion of tag bits of the memory address not matching any entry in the m entries, determine a cache miss; and

in response to the second portion of tag bits of the memory address not matching any entry in the n entries in the second structure, determine a cache miss.

10. The IC of claim 9 , wherein the second circuit to:

in response to the second portion of tag bits of the memory address matching an entry in the n entries in the second structure, determine a cache hit.

11. The IC of claim 10 , wherein the second circuit to:

in response to determining a cache hit, using the offset to retrieve a word from a cache entry corresponding to the matching entry in the n entries in the second structure.

12. The IC of claim 8 , wherein matching the portion of tag bits of the memory address with the m entries in the first structure comprises matching each bit of the first portion of tag bits with a corresponding bit of each entry in the first set of entries.

13. The IC of claim 8 , further comprising:

a third circuit to:

receive a memory block, wherein the memory block corresponds to a first tag and a first index;

store a first subset of tag bits of the first tag in the first structure based on the first index; and

store a second subset of tag bits of the first tag in the second structure based on the first index.

14. The IC of claim 13 , wherein the third circuit to:

store the memory block in the first circuit.

15. An apparatus, comprising:

a processor;

a main memory; and

a m-way set-associative cache coupled to the processor and the main memory, the m-way set-associative cache comprising:

a first circuit to store a set of cache entries, wherein each cache entry includes one or more words of data, wherein each word of data corresponds to a memory address, and wherein the memory address is partitioned into a tag, an index, and an offset;

a first structure to store a first subset of tag bits corresponding to the set of cache entries;

a second structure to store a second subset of tag bits corresponding to the set of cache entries; and

a second circuit to:

use the index to select m entries in the first structure;

match a first portion of tag bits of the memory address with the m entries in the first structure by matching each bit of the first portion of tag bits with a corresponding bit of each entry in the m entries in the first structure;

in response to the first portion of tag bits of the memory address matching n entries in the first structure, where n is less than m, match a second portion of tag bits of the memory address with n entries in the second structure corresponding to the n entries in the first structure; and

wherein the matching the first portion of tag bits of the memory address with the m entries in the first structure and the matching the second portion of tag bits of the memory address with n entries in the second structure is performed in a single clock cycle.

16. The apparatus of claim 15 , wherein the second circuit to:

determine a cache miss in response to the first portion of tag bits of the memory address not matching any entry in the m entries; and

determine a cache miss in response to the second portion of tag bits of the memory address not matching any entry in the n entries in the second structure.

17. The apparatus of claim 16 , wherein the second circuit to:

determine a cache hit in response to the second portion of tag bits of the memory address matching an entry in the n entries in the second structure.

18. The apparatus of claim 17 , wherein the second circuit to:

use the offset to retrieve a word from a cache entry corresponding to the matching entry in the n entries in the second structure in response to determining a cache hit.

19. The apparatus of claim 15 , wherein the m-way set-associative cache further comprising:

a third circuit to:

receive a memory block, wherein the memory block corresponds to a first tag and a first index;

store a first subset of tag bits of the first tag in the first structure based on the first index; and

store a second subset of tag bits of the first tag in the second structure based on the first index.

20. The apparatus of claim 19 , wherein third circuit to:

store the memory block in the first circuit.