Device and method of implementing subpass interleaving of tiled image rendering
Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.
1. A method of tiled image rendering comprising;
dividing a frame to be rendered into a plurality of tiles;
allocating a respective memory address to each of the plurality of the tiles and a memory address for a pushed out tile,
receiving commands to execute a plurality of subpasses of the tiles;
interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations:
storing visibility data for each of the plurality of the tiles that have an adjacent tile in a first direction of traversal at the respective memory addresses allocated for the adjacent tile, wherein the visibility data for a respective tile among the plurality of tiles without a respective adjacent tile in the first direction is stored at the memory address for the pushed out tile, and
rendering the tiles for subsequently ordered subpasses using the visibility data stored at memory addresses allocated for corresponding adjacent tiles and the pushed out tile in a second direction of traversal, opposite the first direction of traversal.
2. The method of claim 1 , further comprising identifying the subpasses by a subpass identifier.
3. The method of claim 1 , further comprising storing the visibility data of the tiles for the subpasses during a visibility generation phase.
4. The method of claim 1 , wherein the first direction of traversal is a forward direction of traversal.
5. The method of claim 1 , wherein the first direction of traversal is a backward direction of traversal.
6. The method of claim 1 , further comprising storing visibility data of one or more pushed out tiles at additional reserved memory addresses.
7. The method of claim 1 , wherein the first direction of traversal is a forward direction of traversal and the second direction of traversal is a backward direction of traversal.
8. The method of claim 1 , wherein the subpasses are executed in an order in which subpass commands are issued.
9. The method of claim 1 , wherein the subpasses are identified by a subpass identifier and during a rendering phase, each subpass comprises a plurality of execution iterations, and
the method further comprises determining, which of the tiles to render according to a corresponding execution iteration and a corresponding subpass identifier.
10. A processing device used for tiled image rendering comprising:
memory; and
a processor configured to:
divide a frame to be rendered into a plurality of tiles;
allocate a respective memory address of the memory to each of the plurality of the tiles and a memory address of the memory for a pushed out tile,
receive commands to execute a plurality of subpasses of the tiles;
interleave execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations:
store visibility data for each of the plurality of the tiles that have an adjacent tile in a first direction of traversal at the respective memory addresses allocated for the adjacent tile, wherein the visibility data for a respective tile among the plurality of tiles without a respective adjacent tile in the first direction is stored at the memory address for the pushed out tile, and
render the tiles for subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for data of corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.
11. The processing device of claim 10 , wherein the processor is configured to identify each of the subsequently ordered subpasses by a subpass identifier.
12. The processing device of claim 10 , wherein the processor is configured to store the visibility data of the tiles for the subsequently ordered subpasses during a visibility generation phase.
13. The processing device of claim 10 , wherein the first direction of traversal is a forward direction of traversal and the corresponding adjacent tiles are corresponding immediately subsequent tiles.
14. The processing device of claim 10 , wherein the first direction of traversal is a backward direction of traversal and the corresponding adjacent tiles are corresponding immediately preceding tiles.
15. The processing device of claim 10 , wherein the processor is configured to store visibility data of one or more pushed out tiles at additional reserved memory addresses.
16. The processing device of claim 10 , wherein the first direction of traversal is a forward direction of traversal and the second direction of traversal is a backward direction of traversal.
17. The processing device of claim 10 , wherein the subpasses are executed in an order in which subpass commands are issued.
18. The processing device of claim 10 , wherein:
the subpasses are identified by a subpass identifier and each subpass comprises a plurality of execution iterations during a rendering phase, and
the processor is further configured to determine, which of the tiles to render according to a corresponding execution iteration and a corresponding subpass identifier.
19. A non-transitory computer readable medium comprising instructions for causing a computer to execute a method of tiled image rendering, the instructions comprising:
dividing a frame to be rendered into a plurality of tiles;
allocating a respective memory address to each of the plurality of the tiles and a memory address for a pushed out tile,
receiving commands to execute a plurality of subpasses of the tiles;
interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations:
storing visibility data for each of the plurality of the tiles that have an adjacent tile in a first direction of traversal at the respective memory addresses allocated for the adjacent tile, wherein the visibility data for a respective tile among the plurality of tiles without a respective adjacent tile in the first direction is stored at the memory address for the pushed out tile, and
rendering the tiles for subsequently ordered subpasses using the visibility data stored at memory addresses allocated for corresponding adjacent tiles and the pushed out tile in a second direction of traversal, opposite the first direction of traversal.
20. The non-transitory computer readable medium of claim 19 , wherein the instructions further comprise identifying each of the subsequently ordered subpasses by a subpass identifier.