Granted Patent B2

US 12,602,532 · App. 17/957,621 · Granted Apr 14, 2026

Inventors: Xiaoqing Xu (Mountain View, CA); Dino Ruic (Santa Clara, CA)

Assignee: GDM Holding LLC

G06F30/398G06F30/394

Abstract

Claims (66)

1 . A computer-implemented method for designing an integrated circuit using transistor placement optimization, the method comprising:

receiving, by a computing system, a specification for the integrated circuit, wherein the specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors;

determining, by the computing system, an initial location and an orientation on a canvas for each transistor in the plurality of transistors;

using, by the computing system, an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors;

using, by the computing system, a local refinement technique to optimize the rough placement to generate a fine placement;

using, by the computing system, a routing technique to generate a routing for the fine placement to generate a completed design; and

storing, by the computing system, the completed design in a layout data store.

2 . The computer-implemented method of claim 1 , further comprising providing the completed design to a fabrication system for fabrication of the integrated circuit.

3 . The computer-implemented method of claim 1 , further comprising:

generating a user interface based on at least one of the rough placement, the fine placement, and the completed design;

receiving a query, via the user interface, that includes one or more query terms; and

updating the user interface to visually emphasize at least one of a subset of transistors or a subset of nets that match the query terms.

4 . The computer-implemented method of claim 3 , further comprising:

receiving, via the user interface, an instruction to add a transistor, remove a transistor, modify the netlist, modify a location of a transistor, modify an orientation of a transistor, or add a region fence around a group of transistors; and

updating at least one of the rough placement, the fine placement, and the completed design based on the instruction.

5 . The computer-implemented method of claim 1 , wherein using the objective function to generate a rough placement having globally optimized locations and orientations for the plurality of transistors includes:

using a simulated annealing technique to optimize locations of the plurality of transistors in a discrete coordinate space.

6 . The computer-implemented method of claim 5 , wherein at least one move of the simulated annealing technique includes modifying an orientation of at least one transistor.

7 . The computer-implemented method of claim 1 , wherein the objective function comprises a weighted half-perimeter wire length (HPWL) function.

8 . A computer-implemented method for designing an integrated circuit using transistor placement optimization, the method comprising:

receiving, by a computing system, a specification for the integrated circuit, wherein the specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors;

determining, by the computing system, an initial location and an orientation on a canvas for each transistor in the plurality of transistors;

using, by the computing system, an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors;

using, by the computing system, a local refinement technique to optimize the rough placement to generate a fine placement;

using, by the computing system, a routing technique to generate a routing for the fine placement to generate a completed design; and

storing, by the computing system, the completed design in a layout data store;

wherein using the objective function to generate the rough placement having globally optimized locations and orientations for the plurality of transistors includes:

using an analytic technique to optimize locations of the plurality of transistors in a continuous coordinate space; and

creating a preliminary discrete layout by converting the optimized locations of the plurality of transistors in the continuous coordinate space to locations in a discrete coordinate space.

9 . The computer-implemented method of claim 8 , wherein converting the optimized locations of the plurality of transistors in the continuous coordinate space to locations in the discrete coordinate space includes:

creating a sorted list of the plurality of transistors for each dimension of the canvas, wherein the sorted list is arranged by the location in a corresponding dimension of the optimized location of each transistor; and

placing the plurality of transistors in the discrete coordinate space according to the sorted lists.

10 . The computer-implemented method of claim 8 , wherein the analytic technique includes a gradient descent technique.

11 . A non-transitory computer-readable medium having computer-executable instructions stored thereon that, in response to execution by one or more processors of a computing system, cause the computing system to perform actions for designing an integrated circuit using transistor placement optimization, the actions comprising:

receiving, by the computing system, a specification for the integrated circuit, wherein the specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors;

determining, by the computing system, an initial location and an orientation on a canvas for each transistor in the plurality of transistors;

using, by the computing system, an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors;

using, by the computing system, a local refinement technique to optimize the rough placement to generate a fine placement;

using, by the computing system, a routing technique to generate a routing for the fine placement to generate a completed design; and

storing, by the computing system, the completed design in a layout data store.

12 . The non-transitory computer-readable medium of claim 11 , wherein the actions further comprise providing the completed design to a fabrication system for fabrication of the integrated circuit.

13 . The non-transitory computer-readable medium of claim 11 , wherein the actions further comprise:

generating a user interface based on at least one of the rough placement, the fine placement, and the completed design;

receiving a query, via the user interface, that includes one or more query terms; and

updating the user interface to visually emphasize at least one of a subset of transistors or a subset of nets that match the query terms.

14 . The non-transitory computer-readable medium of claim 13 , wherein the actions further comprise:

receiving, via the user interface, an instruction to add a transistor, remove a transistor, modify the netlist, modify a location of a transistor, modify an orientation of a transistor, or add a region fence around a group of transistors; and

updating at least one of the rough placement, the fine placement, and the completed design based on the instruction.

15 . The non-transitory computer-readable medium of claim 11 , wherein using the objective function to generate a rough placement having globally optimized locations and orientations for the plurality of transistors includes:

using a simulated annealing technique to optimize locations of the plurality of transistors in a discrete coordinate space.

16 . The non-transitory computer-readable medium of claim 15 , wherein at least one move of the simulated annealing technique includes modifying an orientation of at least one transistor.

17 . The non-transitory computer-readable medium of claim 11 , wherein the objective function comprises a weighted half-perimeter wire length (HPWL) function.

18 . A non-transitory computer-readable medium having computer-executable instructions stored thereon that, in response to execution by one or more processors of a computing system, cause the computing system to perform actions for designing an integrated circuit using transistor placement optimization, the actions comprising:

receiving, by the computing system, a specification for the integrated circuit, wherein the specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors;

determining, by the computing system, an initial location and an orientation on a canvas for each transistor in the plurality of transistors;

using, by the computing system, an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors;

using, by the computing system, a local refinement technique to optimize the rough placement to generate a fine placement;

using, by the computing system, a routing technique to generate a routing for the fine placement to generate a completed design; and

storing, by the computing system, the completed design in a layout data store

wherein using the objective function to generate the rough placement having globally optimized locations and orientations for the plurality of transistors includes:

using an analytic technique to optimize locations of the plurality of transistors in a continuous coordinate space; and

creating a preliminary discrete layout by converting the optimized locations of the plurality of transistors in the continuous coordinate space to locations in a discrete coordinate space.

19 . The non-transitory computer-readable medium of claim 18 , wherein converting the optimized locations of the plurality of transistors in the continuous coordinate space to locations in the discrete coordinate space includes:

creating a sorted list of the plurality of transistors for each dimension of the canvas, wherein the sorted list is arranged by the location in a corresponding dimension of the optimized location of each transistor; and

placing the plurality of transistors in the discrete coordinate space according to the sorted lists.

20 . The non-transitory computer-readable medium of claim 18 , wherein the analytic technique includes a gradient descent technique.

Assignments (2)

Continuity (2)

References Cited (38)