Semiconductor device having an etching stopper layer on a first insulation layer
According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.
1 . A semiconductor device comprising:
an insulating substrate;
a semiconductor layer provided above the insulating substrate, and comprising a source area, a drain area, and a channel area in which a resistance is higher than resistances of the source area and the drain area;
a first insulating layer which covers the semiconductor layer;
an etching stopper layer provided on the first insulating layer, located immediately above the channel area, and being thinner than the first insulating layer;
a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer;
a gate electrode provided on the second insulating layer;
a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and is in contact with the first insulating layer immediately above the source area and immediately above the drain area;
a source electrode which is in contact with the source area in a first contact hole penetrating the first insulating layer and the third insulating layer, and
a drain electrode which is in contact with the drain area in a second contact hole penetrating the first insulating layer and the third insulating layer, wherein
each of the etching stopper layer and the third insulating layer is formed of a material different from the first insulating layer,
the etching stopper layer is formed of a material different from the second insulating layer,
the source electrode and the drain electrode are spaced apart from the etching stopper layer,
the first insulating layer includes a bottom surface and a top surface,
the bottom surface is in contact with the semiconductor layer,
the top surface is in contact with the etching stopper layer and the third insulating layer,
a side surface of the second insulating layer and a side surface of the etching stopper layer are located between the source electrode and the drain electrode, and
the third insulating layer is in contact with the side surface of the second insulating layer and the side surface of the etching stopper layer.
2 . The semiconductor device of claim 1 , wherein
the side surface of the second insulating layer is located immediately above the side surface of the etching stopper layer, and
a side surface of the gate electrode is located immediately above the side surface of the second insulating layer.
3 . The semiconductor device of claim 1 , wherein
the semiconductor layer is an oxide semiconductor layer or a polycrystalline silicon layer, and
an impurity concentration of each of the source area and the drain area is higher than an impurity concentration of the channel area.
4 . The semiconductor device of claim 1 , wherein
a thickness of the first insulating layer is greater than or equal to 70 nm and less than or equal to 100 nm.
5 . The semiconductor device of claim 1 , wherein
a thickness of the etching stopper layer is greater than or equal to 10 nm.
6 . The semiconductor device of claim 1 , wherein
a thickness of the second insulating layer is greater than or equal to 100 nm.
7 . The semiconductor device of claim 1 , wherein
the second insulating layer is a single-layer body of silicon oxide, a single-layer body of silicon nitride or a stacked layer body of a silicon oxide layer and a silicon nitride layer.