IP Library Granted Patent US 12,360,939
Granted Patent B2
US 12,360,939 · App. 17/959,541 · Granted Jul 15, 2025

Data transmission method according to inter-integrated circuit protocol and transmission apparatus

Inventors: Pengxin Bao (Chengdu, CN); Xingxin Zhang (Chengdu, CN); Chao Li (Chengdu, CN); Xuehuan Wang (Chengdu, CN)
Assignee: SHENZHEN YINWANG INTELLIGENT TECHNOLOGIES CO., LTD.
G06F13/4282G06F2213/0016
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Quick Facts
Patent No.
US 12,360,939
App. No.
17/959,541
Granted
Jul 15, 2025
Kind
B2
Abstract

A data transmission method according to an I2C protocol and a transmission apparatus includes: a first transmission chip obtains I2C data from a first device, wherein the I2C data is data sent by the first device to a second device. The first transmission chip sends first feedback information to the first device, wherein the first feedback information is used to indicate whether the I2C data is successfully received. The first transmission chip forwards the I2C data to a second transmission chip corresponding to the second device. The first transmission chip receives second feedback information from the second transmission chip, and the second feedback information is used to indicate whether the I2C data is successfully received. The first transmission chip stores the second feedback information in a first storage space that is storage space of the first transmission chip.

Claims (39)

1. A transmission apparatus, corresponding to a first device, comprising:

a transceiver configured to:

obtain first inter-integrated circuit (I2C) data generated by the first device, wherein the first I2C data is data sent by the first device to a second device;

in response to obtaining, at the transceiver, the first I2C data generated by the first device and adhering to an I2C protocol, send first feedback information from the transceiver to the first device, wherein the first feedback information is used to indicate whether the first I2C data is successfully received;

obtain at least one second I2C data generated by the first device, wherein the at least one second I2C data is data sent by the first device to the second device;

in response to obtaining, at the transceiver, the at least one second I2C data, send another feedback information from the transceiver to the first device, wherein the another feedback information is used to indicate whether the at least one second I2C data is successfully received;

subsequent to obtaining both the first I2C data and the at least one second I2C data, forward both the first I2C data and the at least one second I2C data to a second transmission chip corresponding to the second device; and

receive second feedback information from the second transmission chip, wherein the second feedback information is used to indicate whether the first I2C data and the at least one second I2C data are successfully received at the second device; and

a processor configured to store the second feedback information in first storage space, wherein the first storage space is storage space of the transmission apparatus.

2. The transmission apparatus according to claim 1 , wherein after an amount of I2C data, comprising the first I2C data and the at least one second I2C data, is stored in a second storage space that meets a preset condition, the transceiver is configured to forward the stored I2C data to the second transmission chip, wherein the second storage space is storage space of the transmission apparatus, and the stored I2C data is from the first device.

3. The transmission apparatus according to claim 1 , wherein the transceiver is configured to receive third feedback information from the second transmission chip, wherein the third feedback information is used to indicate the second feedback information respectively corresponding to one or more pieces of I2C data comprising the first I2C data and the at least one second I2C data.

4. The transmission apparatus according to claim 2 , wherein after the transceiver receives the second feedback information from the second transmission chip, the processor is further configured to set the second storage space to a write-inhibit state.

5. The transmission apparatus according to claim 2 , wherein the transceiver is configured to read the I2C data stored in the second storage space.

6. The transmission apparatus according to claim 1 , wherein the first device is a master device and the second device is a slave device, or the first device is a slave device and the second device is a master device.

7. A transmission apparatus, corresponding to a second device, comprising:

a processor; and

a transceiver configured to:

receive inter-integrated circuit (I2C) data, comprising first I2C data and at least one second I2C data, from a first transmission chip corresponding to a first device that generated the first device via an I2C protocol, wherein the first transmission chip is enabled to send first feedback information to the first device in response to the first transmission chip receiving the first I2C data from the first device, and send another feedback information to the first device in response to the first transmission chip receiving the first I2C data from the first device;

send the first I2C data and the at least one second I2C data to the second device;

receive second feedback information from the second device, wherein the second feedback information is used to indicate whether the first I2C data and the at least one second I2C data are successfully received at the second device; and

send the second feedback information to the first transmission chip.

8. The transmission apparatus according to claim 7 , wherein the transceiver is configured to send third feedback information to the first transmission chip, wherein the third feedback information is used to indicate the second feedback information respectively corresponding to one or more pieces of I2C data comprising the first I2C data and the at least one second I2C data.

9. The transmission apparatus according to claim 8 , wherein the transceiver is configured to send the third feedback information to the first transmission chip when a preset trigger condition is met, wherein:

the preset trigger condition is that an amount of the second feedback information meets a preset condition; and/or

the preset trigger condition is that at least one piece of the I2C data fails to be received.

10. The transmission apparatus according to claim 7 , wherein the processor is configured to store the first I2C data and the at least one second I2C data from the first transmission chip in third storage space, wherein the third storage space is storage space of the transmission apparatus.

11. The transmission apparatus according to claim 7 , wherein the first device is a master device and the second device is a slave device, or the first device is a slave device and the second device is a master device.

12. A communications apparatus, comprising:

a processor; and

a transceiver configured to:

send first inter-integrated circuit (I2C) data via an I2C protocol to a first transmission chip corresponding to the communications apparatus;

receive first feedback information from the first transmission chip, wherein the first feedback information is used to indicate whether the first I2C data is successfully received, and wherein the first transmission chip is enabled to send the first feedback information in response to receiving the first I2C data;

send at least one second I2C data via the I2C protocol to the first transmission chip corresponding to the communications apparatus;

receive another feedback information from the first transmission chip, wherein the another feedback information is used to indicate whether the at least one second I2C data is successfully received, and wherein the first transmission chip is enabled to send the another feedback information in response to receiving the at least one second I2C data; and

read first storage space corresponding to the first transmission chip to obtain second feedback information, wherein the second feedback information is used to indicate whether the first I2C data and the at least one second I2C data are successfully received at a second communications apparatus.

13. The communications apparatus according to claim 12 , wherein the transceiver is configured to periodically read the first storage space.

14. The communications apparatus according to claim 12 , wherein the processor is configured to determine that second storage space corresponding to the first transmission chip is in a write-inhibit state.

15. The communications apparatus according to claim 12 , wherein after an amount of I2C data, comprising the first I2C data and the at least one second I2C data, is stored in a second storage space that meets a preset condition, the transceiver is configured to forward the stored I2C data to the second communications apparatus, wherein the second storage space is storage space of the transceiver.

16. The communications apparatus according to claim 12 , wherein the transceiver is configured to receive third feedback information from the second communications apparatus, wherein the third feedback information is used to indicate the second feedback information respectively corresponding to one or more pieces of I2C data comprising the first I2C data and the at least one second I2C data.

Assignments (3)
CHANGE OF NAME Recorded Apr 28, 2026
From: SHENZHEN YINWANG INTELLIGENT TECHNOLOGIES CO., LTD.
To: YINWANG INTELLIGENT TECHNOLOGIES CO., LTD.
Reel/Frame 075485/0524 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2024
From: HUAWEI TECHNOLOGIES CO., LTD.
To: SHENZHEN YINWANG INTELLIGENT TECHNOLOGIES CO., LTD.
Reel/Frame 069336/0026 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2023
From: BAO, PENGXIN; ZHANG, XINGXIN; LI, CHAO; WANG, XUEHUAN
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 062600/0033 →
Continuity (2)
Continuation PCTCN2020083441 · Apr 7, 2020
Related Publication 20230021703A1 · Jan 26, 2023
References Cited (28)
US 8558577B1 · Soriano Fosas · 2013 [cited by examiner]
US 20060129370A1 · Unger · 2006 [cited by examiner]
US 20060206636A1 · McLeod · 2006 [cited by applicant]
US 20070250648A1 · Picard et al. · 2007 [cited by applicant]
US 20100238939A1 · Lee · 2010 [cited by examiner]
US 20110103404A1 · Bafra et al. · 2011 [cited by applicant]
US 20150100820A1 · Faulhaber · 2015 [cited by examiner]
US 20160373338A1 · Suzuki · 2016 [cited by examiner]
US 20180173671A1 · Fujiki et al. · 2018 [cited by applicant]
US 20200012611A1 · Van Bourgognie et al. · 2020 [cited by applicant]
CN 102023954A · 2011 [cited by applicant]
CN 102026281A · 2011 [cited by applicant]
CN 102169463A · 2011 [cited by applicant]
CN 102355462B · 2015 [cited by applicant]
CN 104598418A · 2015 [cited by applicant]
CN 105095139A · 2015 [cited by applicant]
CN 105912354A · 2016 [cited by applicant]
CN 105975425A · 2016 [cited by applicant]
CN 109981480A · 2019 [cited by applicant]
CN 209357068U · 2019 [cited by applicant]
CN 209920986U · 2020 [cited by applicant]
JP 2000312220A · 2000 [cited by applicant]
JP 2011044100A · 2011 [cited by applicant]
JP 2015154260A · 2015 [cited by applicant]
JP 2015230672A · 2015 [cited by applicant]
TW 201536605A · 2015 [cited by applicant]
Integrated Circuits, p. 1-9 (Year: 2004). [cited by examiner]
Anonymous: “The I2C-bus specification Version 2.1”, Philips Semiconductors. Product Specification, Jan. 1, 2000, total 46 pages. [cited by applicant]