Application of low-density parity-check codes with codeword segmentation
A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.
1. A low-density parity-check (LDPC) decoder circuit, comprising:
a segment calculator circuit to segment a codeword of length C bits into N non-overlapping segments of C/N bits, where N is an integer greater than one, and compute an expected error rate for the N non-overlapping segments; and
an error correction code (ECC) computation circuit having check nodes, the ECC computation circuit to perform check node computations, including to first perform decode computations for the N non-overlapping segments, on separate C/N bits at a time with the check nodes, including to adjust the decode computations based on the expected error rate for selected segments of the codeword, and then to perform decode computations for the C bits of the codeword together, based on the decode computations for the N non-overlapping segments.
2. The LDPC decoder circuit of claim 1 , wherein the ECC computation circuit is to adjust the decode computations by adjusting a log likelihood ratio (LLR) of a segment of codeword based on the expected error rate.
3. The LDPC decoder circuit of claim 1 , wherein to adjust the decode computations based on the expected error rate comprises the ECC computation circuit to stop performance of computations for one of the N non-overlapping segments in response to all check nodes for the one of the N non-overlapping segments having all zero syndromes.
4. The LDPC decoder circuit of claim 1 , wherein to adjust the decode computations based on the expected error rate comprises the ECC computation circuit to apply variable check-node scaling to selectively adjust a weighting factor for decode computations for one of the N non-overlapping segments based on a class of check nodes associated with the one of the N non-overlapping segments.
5. The LDPC decoder circuit of claim 4 , wherein to selectively adjust the weighting factor based on the class comprises selective adjustment of the weighting factor based on an address of check nodes.
6. The LDPC decoder circuit of claim 1 , wherein to adjust the decode computations based on the expected error rate comprises the ECC computation circuit to apply variable check node weighting to check nodes based on the expected error rate for the decode computations of selected segments of check nodes.
7. The LDPC decoder circuit of claim 6 , wherein to apply the variable check node weighting based on the expected error rate comprises the ECC computation circuit to apply the variable check node weighting based on raw bit error rate (RBER) for selected segments of the C/N bits of the codeword.
8. The LDPC decoder circuit of claim 6 , wherein to apply the variable check node weighting based on the expected error rate comprises the ECC computation circuit to apply the variable check node weighting for check nodes having error rates above a threshold error rate.
9. The LDPC decoder circuit of claim 1 , wherein N equals 4, with four codeword segments of C/4 bits.
10. The LDPC decoder circuit of claim 9 , wherein the ECC computation circuit is further to decode the codeword with one segment of check nodes for each codeword segment of C/4 bits.
11. The LDPC decoder circuit of claim 1 , wherein the ECC computation circuit is to decode one codeword segment of C/N bits, and stop decoding in response to a zero syndrome in the one codeword segment, wherein in response to a non-zero syndrome in the one codeword segment, the ECC computation circuit is to decode all C bits of the codeword with other codeword segments to correct an error in the one codeword segment.
12. The LDPC decoder circuit of claim 1 , wherein the LDPC decoder circuit comprises an LDPC decoder of a memory device.
13. The LDPC decoder circuit of claim 1 , wherein the LDPC decoder circuit comprises an LDPC decoder of a communication subsystem.
14. A method for decoding, comprising:
segmenting a codeword of length C bits into N non-overlapping segments of C/N bits with a low-density parity-check (LDPC) decoder circuit, where N is an integer greater than one;
performing check node computations with the LDPC decoder circuit, including first performing decode computations for the N non-overlapping segments of C/N bits, including adjusting the decode computations based on an expected error rate for selected segments of the codeword; and then,
performing decode computations with the LDPC decoder circuit for the C bits of the codeword together, based on the decode computations for the N non-overlapping segments.
15. The method of claim 14 , wherein adjusting the decode computations based on the expected error rate comprises stopping performance of computations for one of the segments of the codeword and one of the segments of the check nodes in response to all check nodes of the one of the segments of the codeword having all zero syndromes.
16. The method of claim 14 , wherein adjusting the decode computations based on the expected error rate comprises applying variable check node weighting to check nodes based on the expected error rate for the decode computations of selected segments of check nodes, including applying the variable check node weighting for check nodes having error rates above a threshold error rate.
17. The method of claim 14 , wherein after performing decode computations for one segment of C/N bits, stopping decoding in response to a zero syndrome in the one segment, and decoding all C bits of the codeword with other codeword segments to correct an error in the one segment in response to a non-zero syndrome.
18. An apparatus comprising a computer readable storage medium having content stored thereon, which when executed causes a machine having a low-density parity-check (LDPC) decoder circuit to perform a method for decoding including:
segmenting a codeword of length C bits into N non-overlapping segments of C/N bits with the LDPC decoder circuit, where N is an integer greater than one;
performing check node computations as (N+1) segments of check nodes with the LDPC decoder circuit, including first performing decode computations for the N non-overlapping segments with N segments of the check nodes, including adjusting the decode computations based on an expected error rate for selected segments of the codeword; and then,
performing decode computations for the C bits of the codeword with the LDPC decoder circuit, based on the decode computations for the N non-overlapping segments.
19. The apparatus of claim 18 , wherein adjusting the decode computations based on the expected error rate comprises applying variable check node weighting to check nodes based on the expected error rate for the decode computations of selected segments of check nodes, including applying the variable check node weighting for check nodes having error rates above a threshold error rate.
20. The apparatus of claim 18 , wherein after performing decode computations for one segment of C/N bits, stopping decoding in response to a zero syndrome in the one segment, and decoding all C bits of the codeword with other codeword segments to correct an error in the one segment in response to a non-zero syndrome.