Dual digital phase lock loop with unmodulation coupling

1. A semiconductor device comprising:

an analog phase-lock loop (APLL) configured to output a first signal;

a first digital phase-lock loop (DPLL) configured to output a second signal; and

a second DPLL configured to output a third signal, wherein:

a combination of the first signal and the second signal is being used to generate a first output clock signal; and

a difference resulting from a subtraction of the second signal from the third signal is being used to generate a second output clock signal.

2. The semiconductor device of claim 1 , further comprising:

an integer divider configured to:

receive the combination of the first signal and the second signal; and

output the first output clock signal; and

a fractional output divider configured to:

receive the difference and the combination; and

output the second output clock signal.

3. The semiconductor device of claim 1 , further comprising a plurality of fractional output dividers, wherein each one of the plurality of fractional output dividers is configured to output a copy of the second output clock signal.

4. The semiconductor device of claim 1 , further comprising a low pass filter configured to filter the second signal prior to the subtraction of the second signal from the third signal, where a bandwidth of the low pass filter is based on a bandwidth of the APLL.

5. The semiconductor device of claim 1 , further comprising a scaler configured to scale the difference before generation of the second output clock signal.

6. The semiconductor device of claim 1 , further comprising a frequency output divider, wherein frequency output divider comprises:

a multi-modulus divider configured to receive the combination of the first signal and the second signal;

a sigma-delta modulator configured to receive the difference combination of the first signal and the second signal; and

a jitter reduction circuit configured to reduce jitter in the second output clock signal.

7. The semiconductor device of claim 1 , wherein a difference between a bandwidth of the first DPLL and a bandwidth of the second DPLL is less than a predefined threshold.

8. The semiconductor device of claim 1 , wherein the second output clock signal is independent from operations of the first DPLL.

9. An apparatus comprising:

a plurality of transceivers;

a timing circuit configured to:

receive a first reference signal from a first transceiver among the plurality of transceivers;

receive a second reference signal from a second transceiver among the plurality of transceivers;

output a first output clock signal to a second transceiver among the plurality of transceivers; and

output a second output clock signal to a second clock circuit among the plurality of clock circuits,

wherein:

the first output clock signal is based on a combination of a first signal generate by an analog phase-lock loop (APLL) and a second signal generated by a first digital phase-lock loop (DPLL) in the timing circuit; and

the second output clock signal is based on a difference resulting from a subtraction of the second signal from a third signal generates by a second DPLL of the timing circuit.

10. The apparatus of claim 9 , wherein the timing circuit comprises:

an integer divider configured to:

receive the combination of the first signal and the second signal; and

output the first output clock signal; and

a fractional output divider configured to:

receive the difference and the combination; and

output the second output clock signal.

11. The apparatus of claim 9 , wherein the timing circuit comprises a plurality of fractional output dividers, and each one of the plurality of fractional output dividers is configured to output a copy of the second output clock signal.

12. The apparatus of claim 9 , wherein the timing circuit comprises a low pass filter configured to filter the second signal prior to the subtraction of the second signal from the third signal, where a bandwidth of the low pass filter is based on a bandwidth of the APLL.

13. The apparatus of claim 9 , wherein the timing circuit comprises a scaler configured to scale the difference before generation of the second output clock signal.

14. The apparatus of claim 9 , wherein the timing circuit comprises a frequency output divider, wherein frequency output divider comprises:

a multi-modulus divider configured to receive the combination of the first signal and the second signal;

a sigma-delta modulator configured to receive the difference combination of the first signal and the second signal; and

a jitter reduction circuit configured to reduce jitter in the second output clock signal.

15. The apparatus of claim 9 , wherein a difference between a bandwidth of the first DPLL and a bandwidth of the second DPLL is less than a predefined threshold.

16. The apparatus of claim 9 , wherein the second output clock signal is independent from the first reference signal.

17. A method for operating a timing circuit to synchronize a plurality of networks, the method comprising:

operating an analog phase-lock loop (APLL) to output a first signal;

operating a first digital phase-lock loop (DPLL) to output a second signal;

operating a second DPLL to output a third signal;

combining the first signal and the second signal to generate a first output clock signal; and

subtracting the second signal from the third signal to generate a second output clock signal, wherein the second output clock signal is independent from operations of the first DPLL.

18. The method of claim 17 , further comprising:

operating a plurality of fractional output dividers to output a plurality of copies of the second output clock signal.

19. The method of claim 17 , further comprising operating a low pass filter to filter the second signal prior to subtracting of the second signal from the third signal, wherein a bandwidth of the low pass filter is based on a bandwidth of the APLL.

20. The method of claim 17 , wherein a difference between a bandwidth of the first DPLL and a bandwidth of the second DPLL is less than a predefined threshold.