Conversion of a clean unique request to a read unique request by a memory coherency manager circuit
A system and method mitigates conflicts between clean unique requests by receiving a first clean unique request from a first processor core and a second clean unique request from a second processor core. The first clean unique request and the second clean unique request respectively indicate that the first processor core and second processor core request access to a first address of a memory. The memory is coupled to the first processor core and the second processor core. The first clean unique request and the second clean unique request are determined to be associated with the first address. Further, the second clean unique request is converted into a first read unique request based on determining that the first clean unique request and the second clean unique request are associated with the first address. The first read unique requests indicates that the second processor core requests data.
1. A method comprising:
receiving a first clean unique request from a first processor core and a second clean unique request from a second processor core, wherein the first clean unique request and the second clean unique request respectively indicate that the first processor core and second processor core request access to a first address of a memory coupled to the first processor core and the second processor core;
determining, within a memory coherency manager circuit, that the first clean unique request and the second clean unique request are associated with the first address; and
converting the second clean unique request into a first read unique request based on determining that the first clean unique request and the second clean unique request are associated with the first address, wherein the first read unique request indicates that the second processor core requests data associated with the first address.
2. The method of claim 1 , wherein the first processor core is associated with a first cache memory and the second processor core is associated with a second cache memory, and wherein the method further comprises:
outputting the first clean unique request to the first processor core, wherein data associated with the first address is invalidated within the second cache memory based on receiving the first clean unique request; and
outputting a null response from the second processor core to the first processor core based on invalidating the data associated with the first address in the second cache memory.
3. The method of claim 1 further comprising outputting the first read unique request to the first processor core, wherein the first processor core outputs data associated with the first address to the second processor core based on receiving the first read unique request.
4. The method of claim 1 further comprising outputting the first read unique request to a third processor core, wherein the third processor core outputs a null response to the memory coherency manager circuit based on receiving the first read unique request.
5. The method of claim 4 further comprising:
receiving a third clean unique request from the third processor core; and
converting the third clean unique request to a second read unique request.
6. The method of claim 5 further comprising outputting the second read unique request to the first processor core, and the second processor core, wherein the second processor core outputs data associated with the first address to the third processor core based on receiving the second read unique request.
7. The method of claim 6 , further comprising outputting a null response by the first processor core to the memory coherency manager circuit based on receiving the second read unique request.
8. A processing system comprising:
a memory;
processor cores coupled to the memory, the processor cores comprising:
a first processor core configured to output a first clean unique request associated with a first address within the memory, wherein the first clean unique request indicates that that the first processor core requests access to the first address; and
a second processor core configured to output a second clean unique request associated with the first address, wherein the second clean unique request indicates that that the second processor core requests access to the first address; and
a memory coherency manager circuit configured to:
receive the first clean unique request and the second clean unique request;
determine that the first clean unique request and the second clean unique request are associated with the first address; and
convert the second clean unique request into a first read unique request, wherein the first read unique request indicates that the second processor core requests data associated with the first address.
9. The processing system of claim 8 , wherein the memory coherency manager circuit is further configured to:
output the first clean unique request to the first processor core, wherein data associated with the first address is invalidated within a second cache memory of the second processor core based on receiving the first clean unique request, and wherein the second processor core is configured to:
output a null response from the second processor core to the first processor core based on invalidating the data associated with the first address in the second cache memory.
10. The processing system of claim 8 , wherein the memory coherency manager circuit is further configured to output the first read unique request to the first processor core, wherein the first processor core outputs data associated with the first address to the second processor core based on receiving the first read unique request.
11. The processing system of claim 8 , wherein the memory coherency manager circuit is further configured to output the first read unique request to a third processor core of the processor cores, wherein the third processor core is configured to output a null response to the memory coherency manager circuit based on receiving the first read unique request.
12. The processing system of claim 11 , wherein the third processor core is further configured to output a third clean unique request, and wherein the memory coherency manager circuit is further configured to convert the third clean unique request to a second read unique request.
13. The processing system of claim 12 , wherein the memory coherency manager circuit is further configured to output the second read unique request to the first processor core, and the second processor core, wherein the second processor core is further configured to output data associated with the first address to the third processor core based on receiving the second read unique request.
14. The processing system of claim 13 , wherein the first processor core is configured to output a null response to the memory coherency manager circuit based on receiving the second read unique request.
15. A memory coherency manager circuit configured to:
receive a first clean unique request from a first processor core and a second clean unique request from a second processor core, wherein the first clean unique request and the second clean unique request respectively indicate that the first processor core and second processor core request access to a first address of a memory coupled to the first processor core and the second processor core;
determine that the first clean unique request and the second clean unique request are associated with the first address; and
convert the second clean unique request into a first read unique request based on determining that the first clean unique request and the second clean unique request are associated with the first address, wherein the first read unique request indicates that the second processor core requests data associated with the first address.
16. The memory coherency manager circuit of claim 15 , wherein the first processor core is associated with a first cache memory and the second processor core is associated with a second cache memory, and wherein the memory coherency manager circuit is further configured to:
output the first clean unique request to the first processor core, wherein data associated with the first address is invalidated within the second cache memory based on receiving the first clean unique request; and
output a null response from the second processor core to the first processor core based on invalidating the data associated with the first address in the second cache memory.
17. The memory coherency manager circuit of claim 15 , wherein the memory coherency manager circuit is further configured to output the first read unique request to the first processor core, wherein the first processor core is configured to output data associated with the first address to the second processor core based on receiving the first read unique request.
18. The memory coherency manager circuit of claim 15 , wherein the memory coherency manager circuit is further configured to output the first read unique request to a third processor core, wherein the third processor core is configured to output a null response to the memory coherency manager circuit based on receiving the first read unique request.
19. The memory coherency manager circuit of claim 18 further configured to:
receive a third clean unique request from the third processor core; and
convert the third clean unique request to a second read unique request.
20. The memory coherency manager circuit of claim 19 , wherein the memory coherency manager circuit outputs the second read unique request to the first processor core, and the second processor core, wherein the second processor core outputs data associated with the first address to the third processor core based on receiving the second read unique request.