IP Library Granted Patent US 11,762,250
Granted Patent B2
US 11,762,250 · App. 17/963,243 · Granted Sep 19, 2023

Display device and electronic device

Inventors: Susumu Kawashima (Kanagawa, JP); Naoto Kusumoto (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G02F1/13624G02F1/1368G02F1/136286H01L27/1225H01L27/1255G09G3/3225G09G3/3266G09G3/3677G09G2300/0426G09G2300/0465G09G2300/0852G09G2310/0286G09G2320/0233G09G2330/021H04N23/57H10K59/1213H10K59/1216
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Quick Facts
Patent No.
US 11,762,250
App. No.
17/963,243
Granted
Sep 19, 2023
Kind
B2
Abstract

A display device capable of improving image quality is provided. A display device includes a plurality of pixel blocks in a display region. The pixel blocks each include a first circuit and a plurality of second circuits. The first circuit has a function of adding a plurality of pieces of data supplied from a source driver. The second circuit includes a display element and has a function of performing display in accordance with the added data. One pixel has a configuration including one second circuit and an component of the first circuit that is shared. When the first circuit is shared by a plurality of pixels, the aperture ratio can be increased.

Claims (45)

1. A display device comprising a plurality of pixel blocks,

wherein each of the plurality of pixel blocks comprises a first circuit and a plurality of second circuits,

wherein the first circuit and the plurality of second circuits are electrically connected to each other,

wherein each of the plurality of pixel blocks comprises a plurality of pixels,

wherein one of the plurality of pixels comprises a plurality of components of the first circuit, and

wherein a length in a source line direction of the one of the plurality of pixels is larger than a length in the source line direction of another one of the plurality of pixels.

2. The display device according to claim 1 ,

wherein the first circuit comprises a first transistor, a second transistor, and a first capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitor,

wherein the other electrode of the first capacitor is electrically connected to one of a source and a drain of the second transistor,

wherein a gate of the first transistor is electrically connected to a first gate line, and

wherein a gate of the second transistor is electrically connected to a second gate line.

3. The display device according to claim 2 ,

further comprising a third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the other electrode of the first capacitor, and

wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor are electrically connected to each other, and

wherein a gate of the third transistor is electrically connected to a third gate line.

4. The display device according to claim 2 ,

wherein each of the plurality of second circuits comprises the third transistor and a third circuit,

wherein the one of the source and the drain of the third transistor is electrically connected to the one of the source and the drain of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the third circuit, and

wherein the third circuit comprises a display element.

5. The display device according to claim 4 ,

wherein the third circuit comprises a fourth transistor, a second capacitor, and a light-emitting element as the display element,

wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to one electrode of the light-emitting element,

wherein the one electrode of the light-emitting element is electrically connected to one electrode of the second capacitor, and

wherein the other electrode of the second capacitor is electrically connected to the gate of the fourth transistor.

6. The display device according to claim 5 ,

further comprising a fifth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the one electrode of the light-emitting element,

wherein the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor, and

wherein the other of the source and the drain of the fifth transistor is electrically connected to the one electrode of the second capacitor.

7. The display device according to claim 4 ,

wherein the third circuit comprises a liquid crystal element as the display element, and

wherein one electrode of the liquid crystal element is electrically connected to the one of the source and the drain of the third transistor.

8. The display device according to claim 7 ,

further comprising a third capacitor,

wherein one electrode of the third capacitor is electrically connected the one electrode of the liquid crystal element.

9. The display device according to claim 1 ,

further comprising a fourth circuit and a fifth circuit,

wherein the fourth circuit is configured to control the first circuit, and

wherein the fifth circuit is configured to control the plurality of second circuits.

10. The display device according to claim 1 ,

wherein a transistor included in the pixel block comprises metal oxide in a channel formation region, and wherein the metal oxide comprises In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2022
From: KAWASHIMA, SUSUMU; KUSUMOTO, NAOTO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 061372/0760 →
Priority Claims (1)
JP 2018-085668 · Apr 26, 2018 · national
Continuity (2)
Continuation 17047149
Related Publication 20230036898A1 · Feb 2, 2023