Spread spectrum clock generation device
A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval.
1. A spread spectrum clock generation device comprising:
a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal;
a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal;
a latch configured to receive the first comparison signal and the second comparison signal as inputs and output an output signal; and
a delaying circuit configured to receive the output signal, count using the output signal, and output a count value,
wherein the delaying circuit is further configured to output the input signal using higher-order bits of the count value and delay the output signal to have a different delay time for each time interval,
wherein the delaying circuit comprises a channel selector configured to receive the output signal and generate a selection signal,
wherein the channel selector comprises a first counter and a second counter which use the output signal as a clock, and
wherein a length of time interval is determined based on a maximum value of the first counter, and the selection signal is generated based on an output value of the second counter.
2. The spread spectrum clock generation device of claim 1 , wherein the delaying circuit comprises:
a plurality of delay circuits configured to receive the output signal and generate a plurality of delay output signals having different delay times; and
a multiplexer configured to receive the plurality of delay output signals and select one of the plurality of delay output signals in accordance with the selection signal.
3. The spread spectrum clock generation device of claim 1 ,
wherein, when the length of the time interval is determined as K number of cycles of the output signal, a number of bits of the first counter is determined as a natural number greater than or equal to log 2 K, and the maximum value of the first counter is set to K−1.
4. The spread spectrum clock generation device of claim 2 ,
wherein, when a number of the plurality of delay circuits is M, a number of bits of the second counter is determined as a natural number greater than or equal to log 2 M, and a maximum value of the second counter is set to M−1.
5. The spread spectrum clock generation device of claim 2 ,
wherein each of the plurality of delay circuits is implemented as an RC delay circuit or an inverter chain circuit.
6. The spread spectrum clock generation device of claim 1 ,
wherein, when the input signal is greater than the first reference voltage, the first comparator outputs 1 (logic high) as the first comparison signal, and when the input signal is less than the first reference voltage, the first comparator outputs 0 (logic low) as the first comparison signal, and
wherein, when the input signal is greater than the second reference voltage, the second comparator outputs 0 as the second comparison signal, and when the input signal is less than the second reference voltage, the second comparator outputs 1 as the second comparison signal.
7. The spread spectrum clock generation device of claim 1 , wherein the first reference voltage is higher than the second reference voltage.
8. The spread spectrum clock generation device of claim 6 ,
wherein the latch is an SR latch which comprises an R input, an S input, and an output terminal,
wherein, when the R input is 1 and the S input is 0, the output terminal outputs 0, and when the R input is 0 and the S input is 1, the output terminal outputs 1,
wherein the first comparison signal is input as the R input of the latch, and
wherein the second comparison signal is input as the S input of the latch.
9. A spread spectrum clock generation device comprising:
a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal;
a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal;
a latch configured to receive the first comparison signal and the second comparison signal as inputs and output an output signal; and
a delaying circuit comprising a plurality of delay circuits configured to receive the output signal and generate a plurality of delay output signals having different delay times,
wherein the delaying circuit comprises a channel selector configured to receive the output signal and generate a selection signal,
wherein the channel selector comprises a first counter and a second counter which use the output signal as a clock,
wherein a length of time interval is determined based on a maximum value of the first counter, and the selection signal is generated based on an output value of the second counter, and
wherein the delaying circuit is configured to generate the input signal in a form of a triangular wave by delaying the output signal to have a different delay time for each time interval.
10. The spread spectrum clock generation device of claim 9 , wherein the delaying circuit further comprises:
a multiplexer configured to receive the plurality of delay output signals and select one of the plurality of delay output signals in accordance with the selection signal.
11. The spread spectrum clock generation device of claim 9 ,
wherein, when the length of the time interval is determined as K number of cycles of the output signal, a number of bits of the first counter is determined as a natural number greater than or equal to log 2 K, and the maximum value of the first counter is set to K−1.
12. The spread spectrum clock generation device of claim 9 ,
wherein, when a number of the plurality of delay circuits is M, a number of bits of the second counter is determined as a natural number greater than or equal to log 2 M, and a maximum value of the second counter is set to M−1.
13. The spread spectrum clock generation device of claim 9 ,
wherein, when the input signal is greater than the first reference voltage, the first comparator outputs 1 (logic high) as the first comparison signal, and when the input signal is less than the first reference voltage, the first comparator outputs 0 (logic low) as the first comparison signal, and
wherein, when the input signal is greater than the second reference voltage, the second comparator outputs 0 as the second comparison signal, and when the input signal is less than the second reference voltage, the second comparator outputs 1 as the second comparison signal.
14. The spread spectrum clock generation device of claim 9 , wherein the first reference voltage is higher than the second reference voltage.
15. The spread spectrum clock generation device of claim 13 ,
wherein the latch is an SR latch which comprises an R input, an S input, and an output terminal,
wherein, when the R input is 1 and the S input is 0, the output terminal outputs 0, and when the R input is 0 and the S input is 1, the output terminal outputs 1,
wherein the first comparison signal is input as the R input of the latch, and
wherein the second comparison signal is input as the S input of the latch.