Enhanced gate driver
Circuitry and methods for an improved gate driver circuit for power converters. The improved gate driver circuit substantially reduces propagation delay and transition losses in the floating-gate side of the gate driver circuit. One embodiment includes an inverter having an input configured to receive a state transition signal and an output configured to be coupled to a control input of a switching device. The inverter includes a first NFET having a control gate configured to be coupled to the state transition signal, a second NFET having a control gate coupled to the output of a reference circuit, and a PFET having a control gate configured to be coupled to the state transition signal, wherein the output of the inverter is a node between the conduction channels of the first NFET and the second NFET and the conduction channels of the first NFET, second NFET, and PFET are coupled in series.
1. A driver circuit including:
(a) a reference circuit having an input configured to be coupled to an output of a switching device and an output providing a reference voltage based on a voltage present on the output of the switching device; and
(b) an inverter having an input configured to receive a state transition signal and an output configured to be coupled to a control input of the switching device, the inverter including:
(1) a first NFET having a conduction channel configured to be coupled to the output of the switching device, and a control gate configured to be coupled to the state transition signal;
(2) a second NFET having a conduction channel coupled in series with the conduction channel of the first NFET, and a control gate coupled to the reference voltage output of the reference circuit; and
(3) a PFET having a conduction channel configured to be coupled to a first voltage source and being coupled to the conduction channel of the second NFET, and a control gate configured to be coupled to the state transition signal;
wherein the output of the inverter is a node between the conduction channels of the first NFET and the second NFET.
2. The invention of claim 1 , further including a buffer circuit coupled to the input of the inverter and configured to receive the state transition signal.
3. The invention of claim 1 , wherein the switching device is an NFET.
4. The invention of claim 1 , wherein the switching device includes an input configured to be coupled to a second voltage source providing a voltage lower than a voltage of the first voltage source.
5. The invention of claim 1 , further including the switching device.
6. The invention of claim 1 , wherein the reference circuit is configured to provide a regulated voltage to the control gate of the second NFET so as to make the second NFET substantially conductive at the beginning of a low-to-high voltage transition at the control input of the switching device.
7. A driver circuit including:
(a) a reference circuit having an input configured to be coupled to an output of a first switching device, and an output providing a reference voltage based on a voltage present on the output of the switching device;
(b) a first inverter having an input configured to receive a first state transition signal and an output configured to be coupled to a control input of the first switching device, the inverter including:
(1) a first NFET having a conduction channel configured to be coupled to the output of the first switching device, and a control gate configured to be coupled to the first state transition signal;
(2) a second NFET having a conduction channel coupled in series with the conduction channel of the first NFET, and a control gate coupled to the reference voltage output of the reference circuit; and
(3) a first PFET having a conduction channel configured to be coupled to a first voltage source and being coupled to the conduction channel of the second NFET, and a control gate configured to be coupled to the first state transition signal;
wherein the output of the first inverter is a node between the conduction channels of the first NFET and the second NFET; and
(c) a second inverter having an input configured to receive a second state transition signal and an output configured to be coupled to a control input of a second switching device, the inverter including:
(1) a third NFET having a conduction channel configured to be coupled to the output of the second switching device, and a control gate configured to be coupled to the second state transition signal; and
(2) a second PFET having a conduction channel configured to be coupled to a second voltage source and being coupled to the conduction channel of the third NFET, and a control gate configured to be coupled to the second state transition signal;
wherein the output of the second inverter is a node between the conduction channels of the third NFET and the second PFET.
8. The invention of claim 7 , further including at least one buffer circuit coupled to the input of a respective one of the first or second inverters and configured to receive a respective first or second state transition signal.
9. The invention of claim 7 , wherein the first and second switching devices are NFETs.
10. The invention of claim 7 , wherein the first switching device includes an input configured to be coupled to an input voltage source providing a voltage lower than a voltage of the first voltage source.
11. The invention of claim 10 , wherein the second voltage source is derived from the input voltage source.
12. The invention of claim 7 , further including the first and second switching devices.
13. The invention of claim 7 , wherein the reference circuit is configured to provide a regulated voltage to the control gate of the second NFET so as to make the second NFET substantially conductive at the beginning of a low-to-high voltage transition at the control input of the first switching device.
14. A circuit including:
(a) a half-bridge power stage including:
(1) a first switching device having a control input, an output, and a conduction channel coupled to the output of the first switching device and configured to be coupled to an input voltage source; and
(2) a second switching device having a control input, an output, and a conduction channel coupled between the output of the first switching device and the output of the second switching device;
(b) a reference circuit having an input coupled to the output of the first switching device, and an output providing a reference voltage based on a voltage present on the output of the first switching device;
(c) a first inverter having an input configured to receive a first state transition signal and an output coupled to the control input of the first switching device, the inverter including:
(1) a first NFET having a conduction channel coupled to the output of the first switching device, and a control gate configured to be coupled to the first state transition signal;
(2) a second NFET having a conduction channel coupled in series with the conduction channel of the first NFET, and a control gate coupled to the reference voltage output of the reference circuit; and
(3) a first PFET having a conduction channel configured to be coupled to a first voltage source and being coupled to the conduction channel of the second NFET, and a control gate configured to be coupled to the first state transition signal;
wherein the output of the first inverter is a node between the conduction channels of the first NFET and the second NFET; and
(d) a second inverter having an input configured to receive a second state transition signal and an output coupled to the control input of the second switching device, the inverter including:
(1) a third NFET having a conduction channel coupled to the output of the second switching device, and a control gate configured to be coupled to the second state transition signal; and
(2) a second PFET having a conduction channel configured to be coupled to a second voltage source and being coupled to the conduction channel of the third NFET, and a control gate configured to be coupled to the second state transition signal;
wherein the output of the second inverter is a node between the conduction channels of the third NFET and the second PFET.
15. The invention of claim 14 , further including at least one buffer circuit coupled to the input of a respective one of the first or second inverters and configured to receive a respective first or second state transition signal.
16. The invention of claim 14 , wherein the first and second switching devices are NFETs.
17. The invention of claim 14 , wherein the input voltage source provides a voltage lower than a voltage of the first voltage source.
18. The invention of claim 14 , wherein the second voltage source is derived from the input voltage source.
19. The invention of claim 14 , wherein the reference circuit is configured to provide a regulated voltage to the control gate of the second NFET so as to make the second NFET substantially conductive at the beginning of a low-to-high voltage transition at the control input of the first switching device.