System and method for queuing commands in a deep learning processor
A method includes: dequeuing a signal primitive from a signaling command queue in the set of command queues, the signal primitive pointing to a waiting command queue; in response to the signal primitive pointing to the waiting command queue, incrementing a number of pending signal primitives in the signal-wait counter matrix; dequeuing a wait primitive from the waiting command queue, the wait primitive pointing to the signaling command queue; in response to the wait primitive pointing to the signaling command queue, accessing the register to read the number of pending signal primitives; in response to the number of pending signal primitives indicating at least one pending signal primitive: decrementing the number of pending signal primitives; and dequeuing an instruction from the waiting command queue; and dispatching a control signal representing the instruction to a resource.
1. A method for maintaining dependencies between command streams for a multicore processor comprising, at a queue processor comprising a set of command queues and a signal-wait counter matrix:
dequeuing a first wait primitive from a first waiting command queue in the set of command queues, the first wait primitive pointing to a first signaling command queue in the set of command queues;
accessing a first register in the signal-wait counter matrix, the first register storing a first number of pending signal primitives; and
in response to detecting the first number of pending signal primitives representing at least one pending signal primitive:
dequeuing a first instruction from the first waiting command queue; and
dispatching a first control signal representing the first instruction.
2. The method of claim 1 :
further comprising decrementing the first number of pending signal primitives in the first register;
wherein dequeuing the first instruction comprises dequeuing the first instruction subsequent to the first wait primitive, the first instruction assigned to a first resource of the multicore processor; and
wherein dispatching the first control signal comprises dispatching the first control signal to the first resource.
3. The method of claim 1 , further comprising:
dequeuing a first signal primitive from the first signaling command queue, the first signal primitive pointing to the first waiting command queue; and
incrementing the first number of pending signal primitives in the first register, the first register corresponding to the first signaling command queue and the first waiting command queue.
4. The method of claim 3 :
further comprising incrementing a second number of pending signal primitives stored by a second register of the signal-wait counter matrix, the second register corresponding to the first signaling command queue and a second waiting command queue in the set of command queues; and
wherein dequeuing the first signal primitive from the first signaling command queue comprises dequeuing the first signal primitive from the first signaling command queue, the first signal primitive pointing to the first waiting command queue and the second waiting command queue.
5. The method of claim 4 , further comprising:
dequeuing a second wait primitive from the second waiting command queue, the second wait primitive pointing to the first signaling command queue; and
in response to detecting the second number of pending signal primitives representing at least one signal primitive:
decrementing the second number of pending signal primitives in the second register;
dequeuing a second instruction from the second waiting command queue, the second instruction assigned to a second resource of the multicore processor; and
dispatching a second control signal to the second resource representing the second instruction.
6. The method of claim 1 , further comprising:
dequeuing a second signal primitive from a second signaling command queue in the set of command queues, the second signal primitive pointing to the first waiting command queue; and
incrementing a second number of pending signal primitives stored in a second register in the signal-wait counter matrix.
7. The method of claim 6 :
wherein dequeuing the first wait primitive from the first waiting command queue comprises dequeuing the first wait primitive from the first waiting command queue, the first wait primitive pointing to the first signaling command queue and the second signaling command queue;
wherein dequeuing the first instruction from the first waiting command queue comprises dequeuing the first instruction from the first waiting command queue in response to:
detecting the first number of pending signal primitives representing at least one pending signal primitive; and
detecting the second number of pending signal primitives representing at least one pending signal primitive.
8. The method of claim 1 , further comprising:
enqueuing a first command stream in a first command queue in the set of command queues; and
decoding each command in the series of commands as one of:
an instruction assigned to a resource;
a wait primitive pointing to a signaling command queue in the set of command queues; and
a signal primitive pointing to a waiting command queue in the set of command queues.