Varied validity bit placement in tag bits of a memory
A system and method access memory blocks in a memory by receiving a memory transaction request from a processing device. First hash bits of the memory transaction request are compared with second hash bits of a first memory block of a memory. Data associated with the first memory block is output to the processing device based on the comparison of the first hash bits with the second hash bits.
1. A method comprising:
receiving a memory transaction request from a processing device;
comparing, via control circuitry, first hash bits of the memory transaction request with second hash bits of a first memory block of a memory; and
outputting data associated with the first memory block to the processing device based on a validity bit associated with the second hash bits and the comparison of the first hash bits with the second hash bits.
2. The method of claim 1 , wherein the second hash bits are within tag bits of the first memory block and the validity bit is included within the tag bits, and wherein the method further comprises:
determining a hash value from the second hash bits, and
determining that the validity bit of the tag bits is set based on the hash value, wherein a position of the validity bit within the tag bits corresponds to the hash value.
3. The method of claim 2 , further comprising:
comparing tag bits of the memory transaction request with the tag bits of the first memory block based on determining that the validity bit is set and the comparison of the first hash bits and the second hash bits.
4. The method of claim 3 , further comprising:
determining that the first hash bits and third hash bits of a second memory block of the memory are nonmatching, wherein data is obtained from a primary memory based on determining that the first hash bits and the second hash bits are nonmatching.
5. The method of claim 1 , wherein the first hash bits and the second hash bits include two or more bits, wherein bits of the first hash bits and bits of the second hash bits are the same.
6. The method of claim 1 , wherein a position of the first hash bits within tag bits of the memory transaction request and a position of the second hash bits within tag bits of the first memory block are the same.
7. The method of claim 1 further comprising:
storing data within the first memory block by:
determining a hash value from the second hash bits; and
setting the validity bit within tag bits of the first memory block to a value of one, wherein a position of the validity bit corresponds to the hash value.
8. A system comprising:
a processing device; and
a memory comprising memory blocks, the memory configured to:
receive a memory transaction request from the processing device;
compare first hash bits of the memory transaction request with second hash bits of a first memory block of the memory blocks of the memory; and
output data associated with the first memory block based on a validity bit associated with the second hash bits and the comparison of the first hash bits with the second hash bits to the processing device.
9. The system of claim 8 , wherein the second hash bits are within tag bits of the first memory block and the validity bit is included within the tag bits, and wherein the memory is further configured to:
determine a hash value from the second hash bits, and
determine that the validity bit of the tag bits is set based on the hash value, wherein a position of the validity bit within the tag bits corresponds to the hash value.
10. The system of claim 9 , wherein the memory is further configured to:
compare tag bits of the memory transaction request with the tag bits of the first memory block based on determining that the validity bit is set and the comparison of the first hash bits and the second hash bits.
11. The system of claim 10 , wherein the memory is further configured to:
determine that the first hash bits and third hash bits of a second memory block of the memory are nonmatching, wherein data is obtained from a primary memory based on determining that the first hash bits and the second hash bits are nonmatching.
12. The system of claim 8 , wherein the first hash bits and the second hash bits include two or more bits, wherein bits of the first hash bits and bits of the second hash bits are the same.
13. The system of claim 8 , wherein a position of the first hash bits within tag bits of the memory transaction request and a position of the second hash bits within tag bits of the first memory block are the same.
14. The system of claim 8 , wherein the memory is further configured to:
store data within the first memory block by:
determining a hash value from the second hash bits; and
setting the validity bit within tag bits of the first memory block to a value of one, a position of the validity bit corresponds to the hash value.
15. A memory comprising:
memory blocks; and
control circuitry configured to:
obtain data from a primary memory, the data associated with an address:
determine a hash value from first hash bits of the address;
set a validity bit within tag bits of the address to a valid value, a position of the validity bit corresponds to the hash value; and
store the data within a first memory block of the memory blocks.
16. The memory of claim 15 , wherein the control circuitry is further configured to:
receive a memory transaction request from a processing device;
compare second hash bits of the memory transaction request with the first hash bits; and
output data associated with the first memory block based on the comparison of the first hash bits with the second hash bits to the processing device.
17. The memory of claim 16 , wherein the memory is further configured to:
compare tag bits of the memory transaction request with the tag bits of the address based on determining that the validity bit is set and the comparison of the first hash bits and the second hash bits.
18. The memory of claim 16 , wherein the first hash bits and the second hash bits include two or more bits, wherein bits of the first hash bits and bits of the second hash bits are the same.
19. The memory of claim 16 , wherein a position of the first hash bits within tag bits of the address and a position of the second hash bits within tag bits of the memory transaction request are the same.
20. The memory of claim 16 further configured to:
determine that the second hash bits and third hash bits of a second memory block of the memory blocks are nonmatching, wherein data is obtained from the primary memory based on determining that the first hash bits and the second hash bits are nonmatching.