IP Library Granted Patent US 11,916,068
Granted Patent B2
US 11,916,068 · App. 17/977,875 · Granted Feb 27, 2024

Type III-V semiconductor substrate with monolithically integrated capacitor

Inventors: Hyeongnam Kim (Chandler, AZ); Mohamed Imam (Chandler, AZ)
Assignee: Infineon Technologies Austria AG
H01L27/0629H01L27/0605
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Quick Facts
Patent No.
US 11,916,068
App. No.
17/977,875
Granted
Feb 27, 2024
Kind
B2
Abstract

A semiconductor die includes a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction, and a capacitor monolithically formed in the semiconductor die, wherein a dielectric medium of the capacitor includes a first section of the barrier layer.

Claims (16)

1. A semiconductor device, comprising:

a semiconductor die comprising a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction; and

a capacitor monolithically formed in the semiconductor die,

wherein a dielectric medium of the capacitor comprises a first section of the barrier layer.

2. The semiconductor device of claim 1 , wherein the capacitor comprises a first parallel plate capacitor, and wherein a region of the two-dimensional charge carrier gas that is disposed below the first section of the barrier layer forms a first electrode of the first parallel plate capacitor.

3. The semiconductor device of claim 2 , wherein the semiconductor die comprises a first metallization layer disposed over the barrier layer, and wherein a first section of the first metallization layer that is above the first section of the barrier layer forms a second electrode of the first parallel plate capacitor.

4. The semiconductor device of claim 2 , further comprising a first dielectric layer formed over the barrier layer, and wherein the dielectric medium of the capacitor further comprises a first section of the first dielectric layer that is disposed on top of the first section of the barrier layer.

5. The semiconductor device of claim 4 , wherein the first dielectric layer comprises any one or more of: silicon dioxide, silicon nitride, and silicon oxynitride.

6. The semiconductor device of claim 2 , wherein the capacitor further comprises a second parallel plate capacitor connected between the first and second terminals in parallel with the first parallel plate capacitor.

7. The semiconductor device of claim 6 , wherein the second parallel plate capacitor is vertically stacked on top of the first parallel plate capacitor.

8. The semiconductor device of claim 7 , wherein the semiconductor die further comprises a second dielectric layer and a second metallization layer that are each disposed over the barrier layer, and wherein a dielectric medium of the second parallel plate capacitor comprises a first section of the second dielectric layer that is above the first metallization layer.

9. The semiconductor device of claim 8 , wherein a first section of the second metallization layer that is above the first section of the second dielectric layer forms a first electrode of the second parallel plate capacitor, and wherein a second electrode of the second parallel plate capacitor comprises the first section of the first metallization layer.

10. The semiconductor device of claim 8 , wherein the capacitor further comprises a third parallel plate capacitor connected in parallel with the first and second parallel plate capacitors.

11. The semiconductor device of claim 10 , wherein the semiconductor die comprises a third dielectric layer and a third metallization layer that are each disposed over the barrier layer, and wherein a dielectric medium of the third parallel plate capacitor comprises a first section of the third dielectric layer that is above the second metallization layer.

12. The semiconductor device of claim 11 , wherein a first section of the third metallization layer that is above the first section of the third dielectric layer forms a second electrode of the third parallel plate capacitor, and wherein a first electrode of the third parallel plate comprises the first section of the second metallization layer.

13. The semiconductor device of claim 1 , wherein the capacitor comprises a first parallel plate capacitor, and wherein a region of the two-dimensional charge carrier gas that is disposed below the first section of the barrier layer forms a first electrode of the first parallel plate capacitor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2023
From: INFINEON TECHNOLOGIES AMERICAS CORP.
To: INFINEON TECHNOLOGIES AUSTRIA AG
Reel/Frame 063028/0605 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2022
From: KIM, HYEONGNAM; IMAM, MOHAMED
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 061600/0908 →
Continuity (2)
Division 17196258 · Mar 9, 2021
Related Publication 20230049654A1 · Feb 16, 2023