Granted Patent B2

US 12,588,513 · App. 17/978,968 · Granted Mar 24, 2026

Inventors: Bo-An Tsai (Hsinchu City, TW); Shyng-Yeuan Che (Hsinchu County, TW); Shih-Ping Lee (Hsinchu City, TW)

Assignee: Powerchip Semiconductor Manufacturing Corporation

H01L23/576G06F21/79

Abstract

Claims (48)

1 . A physical unclonable function (PUF) generator structure, comprising:

a substrate; and

a PUF generator comprising:

a first electrode layer disposed on the substrate;

a second electrode layer disposed on the first electrode layer;

a first dielectric layer disposed between the first electrode layer and the second electrode layer;

a first contact and a second contact electrically connected to the first electrode layer and separated from each other, wherein in a cross-sectional view, the first contact and the second contact are symmetrically disposed on the first electrode layer; and

a third contact electrically connected to the second electrode layer.

2 . The PUF generator structure according to claim 1 , wherein the first contact and the second contact are located on a same side of the first dielectric layer, the first contact and the third contact are located on different sides of the first dielectric layer, and the second contact and the third contact are located on different sides of the first dielectric layer.

3 . The PUF generator structure according to claim 1 , wherein the first contact, the second contact, and the third contact are located on a same side of the first dielectric layer.

4 . The PUF generator structure according to claim 1 , wherein the first dielectric layer has a plurality of thicknesses.

5 . The PUF generator structure according to claim 1 , wherein the first dielectric layer comprises:

a center portion; and

an edge portion located on two sides of the center portion, wherein a thickness of the edge portion is less than a thickness of the center portion.

6 . The PUF generator structure according to claim 5 , wherein a top-view pattern of the edge portion surrounds a top-view pattern of the center portion.

7 . The PUF generator structure according to claim 5 , wherein a top-view pattern of the edge portion overlaps a top-view pattern of the first contact and a top-view pattern of the second contact.

8 . The PUF generator structure according to claim 5 , wherein the first contact passes through the edge portion to be electrically connected to the first electrode layer, and the second contact passes through the edge portion to be electrically connected to the first electrode layer.

9 . The PUF generator structure according to claim 1 , wherein the first contact and the second contact are directly connected to the first electrode layer, and the third contact is directly connected to the second electrode layer.

10 . The PUF generator structure according to claim 1 , further comprising:

a second dielectric layer disposed between the first electrode layer and the substrate; and

a third dielectric layer disposed on the first electrode layer, the second electrode layer, the first dielectric layer, and the second dielectric layer.

11 . The PUF generator structure according to claim 10 , wherein the first contact and the second contact are disposed in the second dielectric layer, and the third contact is disposed in the third dielectric layer.

12 . The PUF generator structure according to claim 10 , wherein the first contact, the second contact, and the third contact are disposed in the third dielectric layer.

13 . The PUF generator structure according to claim 1 , comprising a PUF generator array, wherein the PUF generator array comprises:

a plurality of the PUF generators arranged in an array;

a first bit line electrically connected to a plurality of the first contacts;

a second bit line electrically connected to a plurality of the second contacts;

a word line electrically connected to a plurality of the third contacts;

a first transistor electrically connected between the first contact and the first bit line; and

a second transistor electrically connected between the second contact and the second bit line.

14 . The PUF generator structure according to claim 13 , wherein the plurality of the PUF generators are arranged in a first direction and a second direction, and the first direction intersects the second direction.

15 . The PUF generator structure according to claim 13 , wherein the PUF generator array comprises a plurality of the first transistors, and two adjacent first transistors located between two adjacent PUF generators share the same first bit line.

16 . The PUF generator structure according to claim 13 , wherein the PUF generator array comprises a plurality of the second transistors, and two adjacent second transistors located between two adjacent PUF generators share the same second bit line.

17 . An operation method of the PUF generator structure according to claim 1 , comprising:

performing an enrollment operation on the PUF generator, wherein the enrollment operation comprises:

applying a first voltage to the first contact;

applying a second voltage to the second contact; and

applying a third voltage to the third contact, wherein

the first voltage is equal to the second voltage, and

the third voltage is greater than the first voltage and the second voltage.

18 . The operation method of the PUF generator structure according to claim 17 , further comprising:

performing an extraction operation on the PUF generator to read a data enrolled in the PUF generator, wherein the extraction operation comprises:

applying a fourth voltage to the first contact;

applying a fifth voltage to the second contact; and

applying a sixth voltage to the third contact, wherein

the fourth voltage is equal to the fifth voltage, and

The sixth voltage is greater than the fourth voltage and the fifth voltage.

19 . The operation method of the PUF generator structure according to claim 18 , wherein the sixth voltage is less than the third voltage.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (16)