IP Library Granted Patent US 12,519,555
Granted Patent B2
US 12,519,555 · App. 17/982,305 · Granted Jan 6, 2026

Synchronizing update of time of day counters using time stamp exchange over a control plane

Inventor: Srisai Rao Seethamraju (Nashua, NH)
Assignee: Skyworks Solutions, Inc.
H04J3/0667H04J3/0632H04J3/0673H04J3/0688H04J3/0697
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Quick Facts
Patent No.
US 12,519,555
App. No.
17/982,305
Granted
Jan 6, 2026
Kind
B2
Abstract

A control plane, available to all of the line cards in a system, is used to exchange time stamps to align the Time of Day counters in the master line cards. The master line cards are locked to a system clock distributed over the backplane by a timing card. The timing card is locked to timing of a slave line card that is synchronized with the grand master. Each master line card synchronizes updating its Time of Day counter based on a time stamp exchange and a local clock locked to the system clock and without the use of a 1 pulse per second signal.

Claims (27)

1 . A method for synchronizing time of day counters comprising:

synchronizing a first time of day counter on a slave line card to grandmaster timing;

synchronizing a second time of day counter on a first master line card to the first time of day counter on the slave line card based on a first time stamp exchange between the slave line card and the first master line card;

performing a second time stamp exchange between the first master line card and a second master line card; and

synchronizing a third time of day counter in the second master line card to the second time of day counter in the first master line card based on the second time stamp exchange between the first master line card and the second master line card while the first master line card maintains synchronization with the slave line card.

2 . The method as recited in claim 1 wherein time stamps exchanged in the first time stamp exchange have a resolution of at least one nanosecond.

3 . The method as recited in claim 1 wherein the first and second time stamp exchanges occur over a control plane.

4 . The method as recited in claim 1 further comprising synchronizing a master time card with a clock signal received from the slave line card.

5 . The method as recited in claim 4 further comprising generating a system clock based on a phase lock loop synchronized to timing of the slave line card.

6 . The method as recited in claim 1 wherein the first master line card and second master line card have local clock signals that are frequency locked to a master timing card.

7 . The method as recited in claim 6 further comprising measuring a roundtrip time for a signal sent between the master timing card and the slave line card.

8 . The method as recited in claim 6 further comprising determining an error offset based on the first time stamp exchange.

9 . The method as recited in claim 6 further comprising updating the second time of day counter based on at least the first time stamp exchange and a system clock received from the master timing card.

10 . The method as recited in claim 1 further comprising improving alignment of a one pulse per second signal that indicates rollover of the first time of day counters with the first time stamp exchange.

11 . An apparatus that synchronizes time of day counters comprising:

a slave line card with a first time of day counter synchronized to grandmaster timing;

a first master line card with a second time of day counter synchronized with the first time of day counter on the slave line card based on a first time stamp exchange between the slave line card and the first master line card; and

a second master line card configured to perform a second time stamp exchange with the first master line card, the second master line card including a third time of day counter synchronized with the second time of day counter in the first master line card based on the second time stamp exchange between the first master line card and the second master line card while the first master line card maintains synchronization with the slave line card.

12 . The apparatus as recited in claim 11 wherein time stamps exchanged in the first time stamp exchange have a resolution of at least one nanosecond.

13 . The apparatus as recited in claim 11 wherein the first and second time stamp exchanges occur over a control plane.

14 . The apparatus as recited in claim 11 further a master time card that is synchronized with a clock signal received from the slave line card.

15 . The apparatus as recited in claim 14 further comprising a system clock that is based on a phase lock loop synchronized with timing of the slave line card.

16 . The apparatus as recited in claim 11 wherein the first master line card and second master line card have local clock signals that are frequency locked to a master timing card.

17 . The apparatus as recited in claim 16 wherein the master timing card measures a roundtrip time for a signal sent between the master timing card and the slave line card.

18 . The apparatus as recited in claim 17 wherein the master timing card determines an error offset based on the first time stamp exchange.

19 . The apparatus as recited in claim 16 wherein the second time of day counter is updated based on at least the first time stamp exchange and a system clock received from the master timing card.

20 . The apparatus as recited in claim 11 further comprising a one pulse per second signal that indicates rollover of the first time of day counter, the one pulse per signal alignment is improved with the first time stamp exchange.

Continuity (3)
Continuation 16235784 · Dec 28, 2018
Provisional Application 62683464 · Jun 11, 2018
Related Publication 20230208543A1 · Jun 29, 2023
References Cited (65)
US 1007639A · Browne · 1911 [cited by applicant]
US 5140611A · Jones · 1992 [cited by applicant]
US 5509038A · Wicki · 1996 [cited by applicant]
US 5644604A · Larson · 1997 [cited by applicant]
US 5964880A · Liu · 1999 [cited by applicant]
US 6760586B1 · Lee · 2004 [cited by applicant]
US 7002996B1 · Dougherty et al. · 2006 [cited by applicant]
US 7079589B1 · Maksimovic · 2006 [cited by applicant]
US 7116743B1 · Wang · 2006 [cited by applicant]
US 7203227B1 · Currivan · 2007 [cited by applicant]
US 7451337B1 · Hewitt · 2008 [cited by applicant]
US 7451339B2 · Smith, Sr. · 2008 [cited by applicant]
US 7535893B1 · Beladakere et al. · 2009 [cited by applicant]
US 7860205B1 · Aweya et al. · 2010 [cited by applicant]
US 7903681B2 · Roberts et al. · 2011 [cited by applicant]
US 8942561B2 · Boyd et al. · 2015 [cited by applicant]
US 9246615B2 · Ellegard et al. · 2016 [cited by applicant]
US 9426762B2 · Ehlers et al. · 2016 [cited by applicant]
US 9479182B1 · Baidas · 2016 [cited by applicant]
US 9628255B1 · Baidas · 2017 [cited by applicant]
US 9860004B2 · Joergensen · 2018 [cited by applicant]
US 9960873B2 · Yang et al. · 2018 [cited by applicant]
US 10075284B1 · Rodrigues · 2018 [cited by applicant]
US 10158444B1 · Darras · 2018 [cited by applicant]
US 10594423B1 · Anand et al. · 2020 [cited by applicant]
US 10715307B1 · Jin · 2020 [cited by applicant]
US 10797686B1 · Terstrup et al. · 2020 [cited by applicant]
US 10917097B1 · Meyer et al. · 2021 [cited by applicant]
US 10951216B1 · Barnette · 2021 [cited by applicant]
US 11061432B2 · Sarda · 2021 [cited by applicant]
US 11088816B1 · Sarda · 2021 [cited by applicant]
US 11088819B1 · Sarda · 2021 [cited by applicant]
US 11496234B2 · Seethamraju · 2022 [cited by applicant]
US 20060020733A1 · Sarda · 2006 [cited by applicant]
US 20060280182A1 · Williams · 2006 [cited by applicant]
US 20070046516A1 · Dombusch · 2007 [cited by applicant]
US 20090024865A1 · Fugaro · 2009 [cited by applicant]
US 20090168808A1 · Cho · 2009 [cited by examiner]
US 20100118894A1 · Aweya et al. · 2010 [cited by applicant]
US 20120300795A1 · Joergensen · 2012 [cited by applicant]
US 20150185759A1 · Hinderer et al. · 2015 [cited by applicant]
US 20160170439A1 · Aweya · 2016 [cited by applicant]
US 20160182217A1 · Hashizume · 2016 [cited by applicant]
US 20170288801A1 · Aweya · 2017 [cited by applicant]
US 20170373824A1 · Mitchler · 2017 [cited by applicant]
US 20190036804A1 · Mihelic et al. · 2019 [cited by applicant]
US 20190379474A1 · Coulter · 2019 [cited by applicant]
US 20200021379A1 · Aweya · 2020 [cited by applicant]
US 20200050575A1 · Mishra · 2020 [cited by applicant]
US 20200285265A1 · Ranganathan · 2020 [cited by applicant]
US 20210297083A1 · Nishikawa · 2021 [cited by applicant]
CN 101146109 · 2008 [cited by applicant]
CN 102291233 · 2011 [cited by applicant]
CN 103684727 · 2014 [cited by applicant]
CN 104378193 · 2015 [cited by applicant]
CN 105706383 · 2016 [cited by applicant]
CN 107294634 · 2017 [cited by applicant]
WO WO2011045300A2 · 2011 [cited by examiner]
Machine translation of WO 2011045300 A2 (Year: 2011). [cited by examiner]
82P33831, Synchronization Management Unit for IEEE 1588 and 10G/40G/100G Synchronous Ethernet, Renesas, Jul. 10, 2018. [cited by applicant]
AN-12149, Implementing an IEEE 1588 V2 on i.MX RT Using PTPd, FreeRTOS, and IsIP TCP/IP stack, NXP Semiconductors, Sep. 2018. [cited by applicant]
Broadcom Corp., “Ethernet time synchronization providing native timing within the network”, White Paper, Oct. 2008, 36 pages. [cited by applicant]
G.8273/Y.1368 (2018)—Amendment 1, Framework of phase and time clocks, ITU-T, Mar. 2020. [cited by applicant]
Renesas, “Synchronization management unit”, 8A34002 Datasheet, Renesas Electronics Corporation, Sep. 8, 2020, 107 pages. [cited by applicant]
Stanton, 802.1AS Tutorial, Intel Corporation, Nov. 13, 2008, 42 pages. [cited by applicant]