IP Library Granted Patent US 12,426,264
Granted Patent B2
US 12,426,264 · App. 17/989,061 · Granted Sep 23, 2025

Semiconductor devices and data storage systems including the same

Inventors: Jinwoo Lee (Suwon-si, KR); Jooheon Kang (Seoul, KR); Donggeon Gu (Hwaseong-si, KR); Doyoon Kim (Hwaseong-si, KR); Yumin Kim (Seoul, KR); Suseong Noh (Suwon-si, KR); Changyup Park (Hwaseong-si, KR); Hyunjae Song (Hwaseong-si, KR); Dongho Ahn (Hwaseong-si, KR); Myunghun Woo (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10B43/27H01L23/5283H10B41/10H10B41/27H10B41/35H10B43/10H10B43/35
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Quick Facts
Patent No.
US 12,426,264
App. No.
17/989,061
Granted
Sep 23, 2025
Kind
B2
Abstract

A semiconductor device includes a lower structure, a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction, and a channel structure in a channel hole passing through the stack structure. The channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole, the channel layer includes a first element, the variable resistance material layer includes a second element, different from the first element, oxygen, and oxygen vacancies, and the data storage material layer includes the first element, the second element, oxygen, and oxygen vacancies.

Claims (65)

1. A semiconductor device comprising:

a lower structure;

a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction; and

a channel structure in a channel hole that passes through the stack structure,

wherein the channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole,

the channel layer includes a first element,

the variable resistance material layer includes a second element, different from the first element, and oxygen, and the variable resistance material layer has oxygen vacancies, and

the data storage material layer includes the first element, the second element, and oxygen, and the data storage material layer has oxygen vacancies.

2. The semiconductor device of claim 1 , wherein the first element includes silicon (Si), and

the second element includes at least one of hafnium (Hf), aluminum (Al), titanium (Ti), or lanthanum (La).

3. The semiconductor device of claim 1 , wherein a first concentration of the oxygen vacancies in the data storage material layer is greater than a second concentration of the oxygen vacancies in the variable resistance material layer.

4. The semiconductor device of claim 1 , wherein the data storage material layer includes a material in which the channel layer and the variable resistance material layer are combined in a ratio of greater than or equal to 1 to 1.6 and less than or equal to 1 to 5.6.

5. The semiconductor device of claim 1 , wherein the channel layer and the data storage material layer have uniform thicknesses.

6. The semiconductor device of claim 1 , wherein a thickness of the data storage material layer is less than a thickness of the variable resistance material layer.

7. The semiconductor device of claim 6 , wherein a thickness of the data storage material layer is in a range of 1 nm to 3 nm, and

a thickness of the variable resistance material layer is in a range of 7 nm to 20 nm.

8. The semiconductor device of claim 1 , wherein

the channel structure further includes a buried insulating layer extending in the first direction, a conductive pad on the buried insulating layer and in contact with the channel layer, and a dielectric layer between the channel layer and the stack structure, and

the variable resistance material layer covers a side surface of and a bottom surface of the buried insulating layer.

9. The semiconductor device of claim 1 , wherein

the channel structure includes first portions on the same height level as the gate layers and second portions on the same height level as the interlayer insulating layers, and

a first distance from a central axis of the channel structure in the first direction to the data storage material layer in each of the first portions is greater than a second distance from the central axis to the data storage material layer in each of the second portions.

10. The semiconductor device of claim 9 , wherein the data storage material layer includes a bent portion in the first portions.

11. The semiconductor device of claim 9 , wherein

the variable resistance material layer includes protrusions protruding from the first portions toward the gate layers, and

the data storage material layer covers the protrusions.

12. The semiconductor device of claim 1 , wherein the gate layers include a first gate portion in a region adjacent to the channel structure, and a remaining second gate portion,

wherein the first gate portion includes doped polysilicon, and

the second gate portion includes a metallic material.

13. The semiconductor device of claim 1 , wherein

the lower structure includes a lower substrate, circuit elements on the lower substrate, and an upper substrate on the circuit elements, and

the channel structure is in contact with the upper substrate and is electrically connected to at least a portion of the circuit elements.

14. A semiconductor device comprising:

a lower structure including a substrate;

a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a vertical direction, perpendicular to the substrate; and

a channel structure in a channel hole passing through the stack structure,

wherein the channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole,

the channel structure includes first portions on the same height level as the gate layers and second portions on the same height level as the interlayer insulating layers,

in a horizontal direction that is perpendicular to the vertical direction, a width of each of the first portions is wider than a width of each of the second portions,

the variable resistance material layer includes a transition metal oxide having oxygen vacancies,

the data storage material layer includes a transition metal-silicon oxide having oxygen vacancies,

the channel layer includes a semiconductor material, and

a first concentration of oxygen vacancies in the data storage material layer is greater than a second concentration of oxygen vacancies in the variable resistance material layer.

15. The semiconductor device of claim 14 , wherein

the channel layer includes a first element,

the variable resistance material layer includes a second element, different from the first element, and oxygen, and

the data storage material layer includes the first element, the second element, and oxygen.

16. The semiconductor device of claim 14 , wherein

the transition metal oxide includes at least one of hafnium oxide (HfOx), aluminum oxide (AlOx), hafnium-aluminum oxide (HfAlOx), titanium oxide (TiOx), or lanthanum oxide (LaOx), and

the semiconductor material includes polysilicon.

17. The semiconductor device of claim 14 , wherein a first thickness of the data storage material layer is less than a second thickness of the variable resistance material layer.

18. The semiconductor device of claim 14 , wherein

the channel hole has a vertical opening extending in the vertical direction, and horizontal openings extending from the vertical opening in the horizontal direction, and

each of the channel layer and the data storage material layer continuously extends along sidewalls of the vertical opening and the horizontal openings.

19. A data storage system comprising:

a semiconductor storage device including a lower substrate, circuit elements on the lower substrate, a lower structure on the circuit elements and including an upper substrate, a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction, the semiconductor storage device further including a channel structure in a channel hole passing through the stack structure, and an input/output pad electrically connected to the circuit elements; and

a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device,

wherein the channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole,

the channel layer includes a first element,

the variable resistance material layer includes a second element, different from the first element, and oxygen, and the variable resistance material layer has oxygen vacancies, and

the data storage material layer includes the first element, the second element and oxygen, and the data storage material layer has oxygen vacancies.

20. The data storage system of claim 19 , wherein

the first element includes silicon (Si),

the second element includes at least one of hafnium (Hf), aluminum (Al), titanium (Ti), or lanthanum (La), and

a first concentration of the oxygen vacancies in the data storage material layer is greater than a second concentration of the oxygen vacancies in the variable resistance material layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2022
From: LEE, JINWOO; KANG, JOOHEON; GU, DONGGEON; KIM, DOYOON; KIM, YUMIN; NOH, SUSEONG; PARK, CHANGYUP; SONG, HYUNJAE; AHN, DONGHO; WOO, MYUNGHUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 061838/0975 →
Priority Claims (1)
KR 10-2021-0162167 · Nov 23, 2021 · national
Continuity (1)
Related Publication 20230165001A1 · May 25, 2023
References Cited (16)
US 10297312B1 · Futase · 2019 [cited by applicant]
US 10340449B2 · Wu et al. · 2019 [cited by applicant]
US 11011700B2 · Matsuo et al. · 2021 [cited by applicant]
US 20070215977A1 · Lee et al. · 2007 [cited by applicant]
US 20140145137A1 · Ju et al. · 2014 [cited by applicant]
US 20150325788A1 · Hashim et al. · 2015 [cited by applicant]
US 20190280005A1 · Bin et al. · 2019 [cited by applicant]
US 20210074914A1 · Lee et al. · 2021 [cited by applicant]
US 20210384258A1 · Hwang · 2021 [cited by applicant]
US 20230013343A1 · Koo · 2023 [cited by examiner]
KR 1020070092502A · 2007 [cited by applicant]
KR 1020190107499A · 2019 [cited by applicant]
KR 102179934B1 · 2020 [cited by applicant]
KR 1020210029870A · 2021 [cited by applicant]
KR 1020210032920A · 2021 [cited by applicant]
Office Action in Korean Appln. No. KR 10-2021-0162167, mailed on Jul. 31, 2025, 16 pages (with Machine Translation). [cited by applicant]