IP Library Granted Patent US 11,942,031
Granted Patent B2
US 11,942,031 · App. 17/989,386 · Granted Mar 26, 2024

Current limiting circuit, display device, and current limiting method

Inventor: Manabu Fujiwara (Tokyo, JP)
Assignee: JOLED INC.
G09G3/3208G09G2310/0286G09G2330/021G09G2330/025
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Quick Facts
Patent No.
US 11,942,031
App. No.
17/989,386
Granted
Mar 26, 2024
Kind
B2
Abstract

A current limiting circuit is a circuit that receives a video signal for a display panel including pixels, and limits current consumption of the pixels. The current limiting circuit includes: a first gain calculation circuit that calculates a first gain for multiplying with the video signal, based on first power consumption that is power consumption of the pixels corresponding to the video signal; a second gain calculation circuit that calculates a second gain for multiplying with the video signal, based on the first power consumption and a rate of change of the first power consumption; a gain selection circuit that selects one of the first gain and the second gain as a gain by which the video signal is to be multiplied; and a gain multiplication circuit that multiplies the video signal by the gain.

Claims (36)

1. A current limiting circuit that receives a video signal for a display panel including pixels, and limits current consumption of the pixels, the current limiting circuit comprising:

a first gain calculation circuit that calculates a first gain for multiplying with the video signal, based on first power consumption that is power consumption of the pixels corresponding to the video signal;

a second gain calculation circuit that calculates a second gain for multiplying with the video signal, based on the first power consumption and a rate of change of the first power consumption;

a gain selection circuit that selects one of the first gain and the second gain as a gain by which the video signal is to be multiplied; and

a gain multiplication circuit that multiplies the video signal by the gain.

2. The current limiting circuit according to claim 1 ,

wherein the gain selection circuit selects the first gain as the gain when the first power consumption is decreasing, and selects the second gain as the gain when the first power consumption is increasing.

3. The current limiting circuit according to claim 2 ,

wherein the gain selection circuit selects, as the gain, a most recently selected one of the first gain and the second gain, when the first power consumption has not changed.

4. The current limiting circuit according to claim 2 ,

wherein the gain selection circuit selects the first gain as the gain when a change over time of the first power consumption cannot be determined.

5. The current limiting circuit according to claim 1 ,

wherein the first gain calculation circuit calculates a first display screen power value that is a prediction value of power consumption of the pixels corresponding to the video signal for one frame, and

the first gain is less than 1 when the first display screen power value is greater than a control target power value, the control target power value being a control target upper limit of power consumption of the pixels.

6. The current limiting circuit according to claim 5 ,

wherein, when the first display screen power value is greater than the control target power value, the first gain is less than or equal to a value obtained by dividing the control target power value by the first display screen power value.

7. The current limiting circuit according to claim 1 ,

wherein the second gain calculation circuit calculates the second gain based on second power consumption that is power consumption of the pixels corresponding to a value obtained by multiplying the video signal by a sensitivity coefficient, and

the sensitivity coefficient is a coefficient that increases with an increase in the rate of change of the first power consumption.

8. The current limiting circuit according to claim 7 ,

wherein the second gain calculation circuit calculates a second display screen power value that is a prediction value of power consumption of the pixels corresponding to a value obtained by multiplying the video signal for one frame by the sensitivity coefficient, and

the second gain is less than 1 when the second display screen power value is greater than a control target power value, the control target power value being a control target upper limit of power consumption of the pixels.

9. The current limiting circuit according to claim 8 ,

wherein, when the second display screen power value is greater than the control target power value, the second gain is less than or equal to a value obtained by dividing the control target power value by the second display screen power value.

10. The current limiting circuit according to claim 1 ,

wherein the first gain calculation circuit and the second gain calculation circuit calculate and output the first gain and the second gain, respectively, for each period shorter than a vertical period of the video signal.

11. The current limiting circuit according to claim 1 ,

wherein the video signal includes a red (R) signal, a green (G) signal, and a blue (B) signal.

12. A display device comprising:

the current limiting circuit according to claim 1 ; and

the display panel.

13. A current limiting method for limiting current consumption of pixels included in a display panel, the current limiting method comprising:

calculating a first gain for multiplying with a video signal for the display panel, based on first power consumption that is power consumption of the pixels corresponding to the video signal;

calculating a second gain for multiplying with the video signal, based on the first power consumption and a rate of change of the first power consumption;

selecting one of the first gain and the second gain as a gain by which the video signal is to be multiplied; and

multiplying the video signal by the gain.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE APPLICATION NUMBERS RECORDED AGAINST, ONE OF WHICH WAS INCORRECTLY TRANSCRIBED; APPLICATION 18475699 WAS RECRDED INCORRECTLY AND SHOULD HAVE BEEN LISTED INSTEAD AS 18475669 PREVIOUSLY RECORDED AT REEL: 67060 FRAME: 252. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 30, 2024
From: JOLED INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 068377/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2024
From: JOLED INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 067060/0252 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2022
From: FUJIWARA, MANABU
To: JOLED INC.
Reel/Frame 061815/0682 →
Priority Claims (1)
JP 2022-010054 · Jan 26, 2022 · national
Continuity (1)
Related Publication 20230237962A1 · Jul 27, 2023