IP Library Granted Patent US 11,991,557
Granted Patent B2
US 11,991,557 · App. 17/989,921 · Granted May 21, 2024

Determining a number of spatial streams and a bandwidth

Inventors: Yaron Alpert (Hod Hasharoni, IL); Laurent Cariou (Milizac, FR); Po-Kai Huang (San Jose, CA); Xiaogang Chen (Hillsboro, OR); Arik Klein (Givaat Shmuel, IL); Danny Ben-Ari (Hasharon Hatichon, IL); Robert J. Stacey (Portland, OR)
Assignee: Intel Corporation
H04W28/06H04L1/0025H04W84/12
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Quick Facts
Patent No.
US 11,991,557
App. No.
17/989,921
Granted
May 21, 2024
Kind
B2
Abstract

Methods, computer readable media, and apparatus for determining a receive (Rx) number of spatial streams (NSS) for different bandwidths (BWs) and modulation and control schemes (MCSs) are disclosed. An apparatus is disclosed comprising processing circuitry configured to decode a supported HE-MCS and a NSS set field, the supported HE-MSC and NSS set field received from an high-efficiency (HE) station. The processing circuitry may be further configured to determine a first maximum value of N receive (Rx) SS for a MCS and a bandwidth (BW), where the first maximum value of N Rx SS is equal to a largest number of Rx SS that supports the MCS for the BW as indicated by the supported HE-MCS and NSS set field; and, determine additional maximum values based on an operating mode (OM) notification frame, and a value of an OM control (OMC) field. Signaling for BW in 6 GHz is disclosed.

Claims (30)

1. An apparatus of

an extremely high throughput (EHT) station (STA), the apparatus comprising memory; and processing circuitry coupled to the memory, the processing circuitry configured to:

decode, from an access point (AP), a first (PHY) protocol data unit (PPDU), the first PPDU comprising an individual/group bit of a media access control (MAC) individual address of the AP, the individual/group bit set to 1 indicating the first PPDU comprises a service field, the service field comprising a scrambler initialization field comprising a bit 0 , a bit 1 , a bit 2 , a bit 3 , a bit 4 , a bit 5 and a bit 6 for initialization, wherein a transmit order indicates the bit 0 is to be transmitted first and a bit 15 is to be transmitted last, and wherein the service field further comprises a bit 7 , wherein if the bit 7 is set to 0, a channel bandwidth (CBW) is 20 MHz, 40 MHz, 80 MHz, 160 MHz, or 80+80 MHz, and if the bit 5 is set to 0, the bit 6 is set to 0, and the bit 7 is set 1, the CBW is 320 MHz, wherein the first PPDU is a non-high throughput (non-HT) or non-HT duplicate PPDU;

encode a second PPDU in response to the first PPDU, the second PPDU encoded in accordance with the CBW; and

configure the EHT STA to transmit the second PPDU.

2. The apparatus of claim 1 , wherein the first PPDU comprises a request to send (RTS) frame.

3. The apparatus of claim 1 , wherein the second PPDU comprises a clear-to-send (CTS) frame.

4. The apparatus of claim 1 , wherein the first PPDU comprises a control frame and the first PPDU is a non-high throughput (non-HT) or a non-HT duplicate PPDU with a bandwidth signaling transmitter address (TA).

5. The apparatus of claim 1 , wherein the first PPDU is a first control frame and is a non-high throughput (non-HT) duplicate PPDU, and wherein the processing circuitry is further configured to:

transmit a second control frame on each of the 20 MHz subchannels of the CBW.

6. The apparatus of claim 1 , wherein the processing circuitry is further configured to:

receive the first PPDU on a primary 20 MHz.

7. The apparatus of claim 1 , wherein the first PPDU was duplicated on each 20 MHz subchannel of the CBW.

8. The apparatus of claim 1 , wherein the processing circuitry is further configured to:

determine the CBW based on a signal field of the PPDU, if the individual/group bit of individual address of the AP is not set to 1.

9. The apparatus of claim 1 , wherein the first PPDU is a first control frame and is a non-high throughput (non-HT) duplicate PPDU, and wherein the processing circuitry is further configured to:

transmit a second control frame on each of the 20 MHz subchannels of the CBW indicated as free.

10. The apparatus of claim 1 , further comprising transceiver circuitry coupled to the processing circuitry, the transceiver circuitry coupled to two or more microstrip antennas for receiving signaling in accordance with a multiple-input multiple-output (MIMO) technique.

11. The apparatus of claim 1 further comprising transceiver circuitry coupled to the processing circuitry, the transceiver circuitry coupled to two or more patch antennas for receiving signaling in accordance with a multiple-input multiple-output (MIMO) technique.

12. A non-transitory computer-readable storage medium that stores instructions for execution by one or more processors of an apparatus for an apparatus for a extremely high throughput (EHT) station (STA), the instructions to configure the one or more processors to:

decode, from an access point (AP), a first (PHY) protocol data unit (PPDU), the first PPDU comprising an individual/group bit of a media access control (MAC) individual address of the AP, the individual/group bit set to 1 indicating the first PPDU comprises a service field, the service field comprising a scrambler initialization field comprising a bit 0 , a bit 1 , a bit 2 , a bit 3 , a bit 4 , a bit 5 and a bit 6 for initialization, wherein a transmit order indicates the bit 0 is to be transmitted first and a bit 15 is to be transmitted last, and wherein the service field further comprises a bit 7 , wherein if the bit 7 is set to 0, a channel bandwidth (CBW) is 20 MHz, 40 MHz, 80 MHz, 160 MHz, or 80+80 MHz, and if the bit 5 is set to 0, the bit 6 is set to 0, and the bit 7 is set 1, the CBW is 320 MHz, wherein the first PPDU is a non-high throughput (non-HT) or non-HT duplicate PPDU;

encode a second PPDU in response to the first PPDU, the second PPDU encoded in accordance with the CBW; and

configure the EHT STA to transmit the second PPDU.

13. An apparatus of an extremely high throughput (EHT) access point (AP), the apparatus comprising memory; and processing circuitry coupled to the memory, the processing circuitry configured to:

decode, from an extremely high throughput (EHT) station (STA), a first (PHY) protocol data unit (PPDU), the first PPDU comprising an individual/group bit of a media access control (MAC) individual address of the EHT STA, the individual/group bit set to 1 indicating the first PPDU comprises a service field, the service field comprising a scrambler initialization field comprising a bit 0 , a bit 1 , a bit 2 , a bit 3 , a bit 4 , a bit 5 and a bit 6 for initialization, wherein a transmit order indicates the bit 0 is to be transmitted first and a bit 15 is to be transmitted last, and wherein the service field further comprises a bit 7 , wherein if the bit 7 is set to 0, a channel bandwidth (CBW) is 20 MHz, 40 MHz, 80 MHz, 160 MHz, or 80+80 MHz, and if the bit 5 is set to 0, the bit 6 is set to 0, and the bit 7 is set 1, the CBW is 320 MHz, wherein the first PPDU is a non-high throughput (non-HT) or non-HT duplicate PPDU;

configure the EHT AP to transmit the first PPDU;

decode a second PPDU in response to the first PPDU, the second PPDU encoded in accordance with the CBW.

14. The apparatus of claim 13 , wherein the processing circuitry is further configured to:

encode the first PPDU to comprise a media access control (MAC) individual address of the EHT AP with an individual/group bit set to 1.

15. The apparatus of claim 13 , wherein the first PPDU comprises a request to send (RTS) frame and the second PPDU comprises a clear-to-send (CTS) frame.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2026
From: INTEL CORPORATION
To: LENOVO IRELAND INTERNATIONAL LIMITED
Reel/Frame 075668/0293 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2026
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 075592/0732 →