Large-format battery management system with in-rush protection using multiple thermistors
A system for suppressing inrush currents is described. The system may include a negative temperature coefficient (NTC) thermistor and a positive temperature coefficient (PTC) thermistor arranged in series between a power source and a battery system to be charged. At a low temperature, while the PTC thermistor provides only minimal resistance to minimize an inrush current, the NTC thermistor provides increased resistance. As the temperature increases, the resistance provided by the PTC thermistor increases as the resistance from the NTC thermistor decreases. The system may be used in conjunction with a battery charging system has at least one current pathway from the power source to the battery system.
1. A device for powering a load comprising:
a power input terminal configured to be connected to a power source;
a power output terminal configured to be connected to a load;
a first conduction path connecting the power input terminal and the power output terminal, wherein the first conduction path comprises one or more first thermistors of a first type of thermistor in series with one or more second thermistors of a second type of thermistor, wherein a first resistance of the first type of thermistor responds, to a change in temperature, in an opposite direction than how a second resistance of the second thermistor responds to the change in temperature;
a second conduction path connecting the power input terminal and the power output terminal; and
a switching circuit configured to connect, during a first time interval and via the first conduction path, the power input terminal and the power output terminal and configured to connect, during a second first time interval and via the second conduction path, the power input terminal and the power output terminal,
wherein, at a beginning of the first time interval, one of the first type of thermistor or second type of thermistor has a greater resistance than a corresponding second or first type of thermistor, and
wherein, at an end of the first time interval, the one of the first type of thermistor or second type of thermistor has a lower resistance than the corresponding second or first type of thermistor.
2. The device of claim 1 ,
wherein the first type of thermistor is a positive temperature control (PTC) thermistor, and
wherein the second type of thermistor is a negative temperature control (NTC) thermistor.
3. The device of claim 1 , wherein the first conduction path further comprises:
a resistor.
4. The device of claim 1 , wherein the switching circuit comprises:
a first transistor with a first control terminal, a first terminal, and a second terminal, wherein the first terminal and the second terminal form a first current path, wherein the first current path is connected between the power input terminal and the first conduction path;
a second transistor with a second control terminal, a third terminal, and a fourth terminal, wherein the third terminal and the fourth terminal form a second current path, wherein the second current path is connected between the power input terminal and the second conduction path; and
a microprocessor configured to selectively enable, during the first time interval, the first transistor and, during a second time interval, the second transistor.
5. The device of claim 4 ,
wherein the first transistor comprises a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a power MOSFET.
6. The device of claim 1 , further comprising:
a second switching circuit configured to connect, during the first time interval, the first conduction path and the power output terminal and, during a second time interval, the second conduction path and the power output terminal.
7. The device of claim 6 , further comprising:
a microprocessor configured to control the switching circuit and the second switching circuit.
8. The device of claim 1 , further comprising:
a resistor electrically connected in the first conduction path.
9. The device of claim 1 ,
wherein, for a first range of temperatures, a series resistance of a combination of the one or more first thermistors and one or more second thermistors includes a minimum series resistance, and
wherein, for temperatures below the first range of temperatures, the series resistance of the combination is above the minimum series resistance.
10. The device of claim 1 ,
wherein, for a first range of temperatures, a series resistance of a combination of the one or more first thermistors and one or more second thermistors includes a minimum series resistance, and
wherein, for temperatures above the first range of temperatures, the series resistance of the combination is above the minimum series resistance.
11. The device of claim 1 ,
wherein the switching circuit comprises a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a power MOSFET.
12. The device of claim 1 ,
wherein the one or more first thermistors comprise two or more thermistors in series or parallel.
13. The device of claim 1 ,
wherein the one or more first thermistors comprise positive temperature compensation (PTC) thermistors or negative temperature compensation (NTC) thermistors.
14. The device of claim 1 ,
wherein the one or more first thermistors comprise at least one thermistor of the first type in series with a parallel combination of two or more thermistors of the first type, and
wherein the one or more first thermistors comprise positive temperature compensation (PTC) thermistors or negative temperature compensation (NTC) thermistors.
15. A method comprising:
receiving, at a switching circuit and at a beginning of a first time interval, a first signal to permit conduction, via a first conductive path, between a power input terminal and a power output terminal and to prevent conduction, via a second conductive path, between the power input terminal and the power output terminal;
permitting, by the switching circuit and based on the first signal, conduction via the first conductive path, wherein a first resistance of the first conductive path is high at a first temperature, high at a second temperature, and low at a third temperature, and wherein the third temperature is between the first temperature and the second temperature;
receiving, at the switching circuit and at an end of the first time interval, a second signal to prevent conduction, via the first conductive path, between a power input terminal and a power output terminal and to permit conduction, via a second conductive path, between the power input terminal and the power output terminal; and
permitting, by the switching circuit and based on the second signal, conduction via the second conductive path, wherein a second resistance of the second conduction path is lower, at the first temperature, than the first resistance, and wherein the second resistance is lower, at the third temperature, than the first resistance.
16. A device comprising:
a first conductive path comprising a series connection of at least one positive temperature control (PTC) thermistor and at least one negative temperature control (NTC) thermistor, wherein the first conductive path is connected to a load;
a second conductive path connected, in parallel with the first conductive path, to the load;
a first switching circuit electrically connected between a power terminal and each of a first conductive path and a second conductive path; and
a microprocessor configured to control the first switching circuit to selectively connect, to the power terminal, the first conductive path or the second conductive path.
17. The device of claim 16 ,
wherein the at least one PTC thermistor comprises two or more PTC thermistors.
18. The device of claim 16 ,
wherein the at least one NTC thermistor comprises two or more NTC thermistors.
19. The device of claim 16 , further comprising:
a second switching circuit electrically connected between a load terminal and each of the first conductive path and the second conductive path,
wherein the second switching circuit is configured to be controlled by the microprocessor to selectively connect, to the load terminal, the first conductive path or the second conductive path.
20. The device of claim 19 ,
wherein the microprocessor is configured to simultaneously control the first switching circuit and the second switching circuit to connect, via the first conductive path or via the second conductive path, the power terminal and the load terminal.