Photonic implementation of message generation for digital currency transactions
Embodiments of the present disclosure are directed to a photonic implementation of a processor for message generation for digital currency (e.g., bitcoin) transactions. The processor includes an input photonic circuit and a message generation photonic circuit coupled to the input photonic circuit via a first set of optical connections. The input photonic circuit receives input data of a first size and splits the received input data into a plurality of input messages of a second size. The message generation photonic circuit receives the plurality of input messages from the input photonic circuit via the first set of optical connections, and generates a plurality of output messages of the second size based at least in part on the plurality of input messages.
1 . A photonic processor, comprising:
an input photonic circuit configured to:
receive input data of a first size, and
split the received input data into a plurality of input messages of a second size;
a message generation photonic circuit directly connected to the input photonic circuit, the message generation photonic circuit configured to:
receive the plurality of input messages from the input photonic circuit, and
generate a plurality of output messages of the second size based at least in part on the plurality of input messages; and
an array of photodetectors directly connected to the message generation photonic circuit, the array of photodetectors configured to:
receive the plurality of output messages from the message generation photonic circuit, and
generate one or more hash values by processing the plurality of output messages.
2 . The photonic processor of claim 1 , wherein the input photonic circuit comprises:
an array of photonic intensity modulators configured to receive the input data from an array of lasers.
3 . The photonic processor of claim 2 , wherein the array of photonic intensity modulators comprises at least one of an array of electro-optic effect modulators, an array of carrier-depletion effect modulators, and an array of thermo-optic effect modulators.
4 . The photonic processor of claim 3 , wherein:
the array of electro-optic effect modulators comprises an array of Mach-Zehnder modulators; and
the array of carrier-depletion effect modulators comprises at least one of an array of micro-disk modulators, an array of nanobeam modulators, and an array of micro-ring modulators.
5 . The photonic processor of claim 2 , wherein:
a first portion of the received input data is associated with a first subset of the input messages that do not comprise parts of a nonce; and
a second portion of the received input data is associated with a second subset of the input messages comprising a plurality of increments of the nonce.
6 . The photonic processor of claim 5 , wherein the first subset of input messages comprises an input message of the plurality of input messages received in a plurality of optical wavelengths.
7 . The photonic processor of claim 5 , wherein each input message in the second subset comprises a respective increment of the nonce represented as a respective optical wavelength of a plurality of optical wavelengths.
8 . The photonic processor of claim 2 , wherein the input photonic circuit further comprises an array of photonic splitters coupled to the array of photonic intensity modulators, the array of photonic splitters configured to:
receive the input data from the array of photonic intensity modulators; and
split the received input data into the plurality of input messages.
9 . The photonic processor of claim 1 , wherein the message generation photonic circuit comprises a plurality of photonic components configured to generate a subset of the plurality of output messages by at least performing rotation and shifting of a subset of the plurality of input messages.
10 . The photonic processor of claim 9 , wherein the plurality of photonic components comprises at least one of: a plurality of three-dimensional layout components, a plurality of three-dimensional bit corrector gates, a plurality of photonic crossing devices, a plurality of photonic logic gates, a plurality of photonic wire bonds, a plurality of optical fibers, a plurality of photonic logic super-gates, and a plurality of photonic regenerator stages.
11 . The photonic processor of claim 1 , wherein the message generation photonic circuit is configured to generate an output message of the plurality of output messages by summing a corresponding pair of processed versions of the plurality of input messages and a corresponding pair of the plurality of input messages.
12 . The photonic processor of claim 1 , wherein the message generation photonic circuit comprises at least one of: a plurality of photonic logic adders, a plurality of bit corrector gates, a plurality of photonic logic super-gates, and a plurality of photonic regenerator stages.
13 . The photonic processor of claim 1 , wherein a number of the plurality of input messages is equal to a ratio of the first size to the second size.
14 . The photonic processor of claim 1 , wherein the photonic processor is implemented as a silicon photonics platform.
15 . A non-transitory computer-readable storage medium comprising stored instructions that, when executed by at least one processor, cause the at least one processor to:
initiate reception of input data of a first size by an input photonic circuit of a photonic processor including an array of lasers and an array of photonic intensity modulators, a first portion of the input data associated with a first subset of a plurality of input messages that do not comprise parts of a nonce, the first subset comprises an input message received in a plurality of optical wavelengths, a second portion of the input data associated with a second subset of the plurality of input messages comprising a plurality of increments of the nonce, each input message in the second subset comprises a corresponding increment of the nonce represented as a corresponding optical wavelength of the plurality of optical wavelengths;
initiate, at the input photonic circuit, splitting of the input data into the plurality of input messages of a second size;
initiate reception of the plurality of input messages at a message generation photonic circuit of the photonic processor directly connected to the input photonic circuit; and
instruct the message generation photonic circuit to generate a plurality of output messages of the second size based at least in part on the plurality of input messages.
16 . The computer-readable storage medium of claim 15 , wherein the stored instructions comprise further stored instructions that, when executed, cause the at least one processor to:
initiate reception of the input data from the array of photonic intensity modulators via an array of photonic splitters of the photonic processor coupled to the array of photonic intensity modulators; and
instruct the array of photonic splitters to split the received input data into the plurality of input messages.
17 . A non-transitory computer-readable storage medium comprising stored instructions that, when executed by at least one processor, cause the at least one processor to:
initiate reception of input data of a first size by an input photonic circuit of a photonic processor;
initiate, at the input photonic circuit, splitting of the input data into a plurality of input messages of a second size;
initiate reception of the plurality of input messages at a message generation photonic circuit of the photonic processor directly connected to the input photonic circuit;
instruct the message generation photonic circuit to generate a plurality of output messages of the second size based at least in part on the plurality of input messages; and
instruct the message generation photonic circuit to generate an output message of the plurality of output messages by summing a corresponding pair of processed versions of the plurality of input messages and a corresponding pair of the plurality of input messages.
18 . A method comprising:
receiving input data of a first size by an input photonic circuit of a photonic processor;
splitting, by the input photonic circuit, the received input data into a plurality of input messages of a second size;
receiving the plurality of input messages at a message generation photonic circuit of the photonic processor directly connected to the input photonic circuit;
generating, by the message generation photonic circuit, a plurality of output messages of the second size based at least in part on the plurality of input messages;
receiving the plurality of output messages at an array of photodetectors directly connected to the message generation photonic circuit; and
processing, by the array of photodetectors, the plurality of output messages to generate one or more hash values.