Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor

1. An apparatus comprising:

a memory interface coupled to a memory;

a data cache;

an instruction cache; and

a plurality of processing circuits, a first processing circuit of the plurality of processing circuits comprising:

a processor core configured to execute a fiber create instruction as a parent execution thread to generate one or more call work descriptor packets to one or more second processing circuits, of the plurality of processing circuits, for execution of one or more child execution threads of a plurality of child execution threads, each call work descriptor packet of the one or more call work descriptor packets comprising a program count and either an argument or a memory address for a corresponding execution thread of the one or more execution threads;

a thread control memory comprising a plurality of registers, the plurality of registers comprising a thread identifier pool register configured to store a plurality of thread identifiers, a program count register configured to store a received program count, and a thread return register; and

a control logic and thread selection circuit configured to schedule the parent, fiber create instruction for execution by the processor core and to reserve a predetermined amount of memory space in the thread control memory based upon a number of return parameters to be generated by each child execution thread, the control logic and thread selection circuit further configured to store a thread return count in the thread return register, the thread return count indicating a count of the one or more child execution threads;

wherein the one or more second processing circuits are configured to:

access data from the data cache;

receive a call work descriptor packet of the one or more call work descriptor packets;

decode the received call work descriptor packet into a received program count and either a received argument or a received memory address, the received program count specifying a thread create instruction indicating the number of return parameters; and

execute instructions from the instruction cache to perform operations comprising:

automatically creating and executing a corresponding child thread in response to the received call work descriptor packet; and

providing access to the return parameters from the reserved memory space to the parent execution thread based at least in part on a thread return instruction from the corresponding child thread.

2. The apparatus of claim 1 , wherein the operations further comprise:

receiving a join instruction from the parent execution thread;

wherein the providing of the access to the return parameters from the reserved memory space to the parent execution thread is in response to the receipt of the join instruction.

3. The apparatus of claim 2 , wherein the thread create instruction further indicates a caller identifier; and the caller identifier is provided to the parent execution thread in response to the receipt of the join instruction.

4. The apparatus of claim 1 , wherein the thread create instruction from the parent execution thread uses a plurality of bits to indicate the number of return parameters.

5. The apparatus of claim 1 , wherein the reserving of the memory space comprises reserving a predetermined number of bits for each return parameter.

6. The apparatus of claim 1 , wherein the providing of the access to the return parameters from the reserved memory space to the parent execution thread comprises copying data from the reserved memory space to a register or register state of the parent thread.

7. The apparatus of claim 1 , wherein the operations further comprise:

in response to the thread return instruction, checking that all operations initiated by the corresponding child thread either have been completed or have been acknowledged.

8. The apparatus of claim 1 , wherein the operations further comprise:

waiting for all threads created by the child execution thread to complete before sending the thread return instruction from the child execution thread.

9. The apparatus of claim 1 , wherein the thread create instruction further indicates whether to start the child execution thread on a local node or a remote node.

10. The apparatus of claim 1 , wherein the creating of the child execution thread further comprises:

beginning execution of the child execution thread from an address read from a register of the parent execution thread.

11. The apparatus of claim 1 , wherein the thread create instruction further indicates a number of call arguments, and the call arguments are accessed from registers of the parent thread.

12. The apparatus of claim 1 , wherein at least one second processing circuit of the one or more second processing circuits is a hybrid threading processor.

13. A non-transitory machine-readable medium that stores a plurality of instructions that, when executed by a plurality of processing circuits, cause the plurality of processing circuits to perform operations comprising:

using a first processing circuit of the plurality of processing circuits, executing a fiber create instruction as a parent execution thread to generate one or more call work descriptor packets to one or more second processing circuits, of the plurality of processing circuits, for execution of one or more child execution threads of a plurality of child execution threads, each call work descriptor packet of the one or more call work descriptor packets comprising a program count and either an argument or a memory address for a corresponding execution thread of the one or more execution threads;

using the first processing circuit, reserving a predetermined amount of memory space in a thread control memory based upon a number of return parameters to be generated by each child execution thread;

using the first processing circuit, storing a thread return count in a thread return register, the thread return count indicating a count of the one or more child execution threads;

using the one or more second processing circuits, receiving a call work descriptor packet of the one or more call work descriptor packets and decoding the received call work descriptor packet into a received program count and either a received argument or a received memory address, the received program count specifying a thread create instruction indicating the number of return parameters;

using the one or more second processing circuits, automatically creating and executing a corresponding child execution thread in response to the receipt of the received call work descriptor packet; and

using the one or more second processing circuits, providing access to the return parameters from the reserved memory space to the parent execution thread based at least in part on a thread return instruction from the child execution thread.

14. The non-transitory machine-readable medium of claim 13 , wherein the operations further comprise:

receiving a join instruction from the parent execution thread;

wherein the providing of the access to the return parameters from the reserved memory space to the parent execution thread is in response to the receipt of the join instruction.

15. The non-transitory machine-readable medium of claim 13 , wherein the thread create instruction from the parent execution thread that indicates the number of return parameters uses a plurality of bits to indicate the number of return parameters and selects one of 0, 1, 2, or 4 parameters.

16. The non-transitory machine-readable medium of claim 13 , wherein the reserving of the memory space comprises reserving a predetermined number of bits for each return parameter.

17. The non-transitory machine-readable medium of claim 13 , wherein the providing of the return parameters from the reserved memory space to the parent execution thread comprises copying data from the reserved memory space to a register or register state of the parent execution thread.

18. The non-transitory machine-readable medium of claim 13 , wherein the operations further comprise:

in response to the thread return instruction, checking that all operations initiated by the child execution thread have either completed or been acknowledged.

19. A method comprising:

using a first processing circuit of a plurality of processing circuits, executing a fiber create instruction as a parent execution thread to generate one or more call work descriptor packets to one or more second processing circuits, of the plurality of processing circuits, for execution of one or more child execution threads of a plurality of child execution threads, each call work descriptor packet of the one or more call work descriptor packets comprising a program count and either an argument or a memory address for a corresponding execution thread of the one or more execution threads;

using the first processing circuit, reserving a predetermined amount of memory space in a thread control memory based upon a number of return parameters to be generated by each child execution thread;

using the first processing circuit, storing a thread return count in a thread return register, the thread return count indicating a count of the one or more child execution threads;

using the one or more second processing circuits, receiving a call work descriptor packet of the one or more call work descriptor packets and decoding the received call work descriptor packet into a received program count and either a received argument or a received memory address, the received program count specifying a thread create instruction indicating the number of return parameters;

using the one or more second processing circuits, automatically creating and executing a corresponding child execution thread in response to the received call work descriptor packet; and

using the one or more second processing circuits, providing access to the return parameters from the reserved memory space to the parent execution thread based at least in part on a thread return instruction from the child execution thread.

20. The method of claim 19 , further comprising:

waiting for all threads created by the child execution thread to complete before sending the thread return instruction from the child execution thread.

21. The method of claim 19 , wherein the thread create instruction further indicates whether to start the child execution thread on a local node or a remote node.

22. The method of claim 19 , wherein the creating of the child execution thread comprises:

beginning execution of the child execution thread from an address read from a register of the parent execution thread.

23. The method of claim 19 , wherein:

the thread create instruction further indicates a number of call arguments; and the call arguments are accessed from registers of the parent execution thread.