Multichip ray tracing device and method
There is provided a multichip ray tracing device. The multichip ray tracing device includes a plurality of memory units; an acceleration structure division processing unit that divides an acceleration structure (AS) into a plurality of divided acceleration structures and stores each of the plurality of divided acceleration structures in a corresponding memory unit among the plurality of memory units; and a plurality of ray tracing core units connected to the plurality of memory units. Each of the plurality of ray tracing core units performs an internal ray tracing (Internal RT) operation for a corresponding divided acceleration structure and transmits corresponding ray information to a corresponding ray tracing core unit to perform an external ray tracing (External RT) operation when attempting to access a data node that is not in the corresponding divided acceleration structure in the process of the internal ray tracing operation.
1. A multichip ray tracing device comprising:
a plurality of memory units;
an acceleration structure division processing unit that divides an acceleration structure (AS) into a plurality of divided acceleration structures and stores each of the plurality of divided acceleration structures in a corresponding memory unit among the plurality of memory units; and
a plurality of ray tracing core units connected to the plurality of memory units, wherein each of the plurality of ray tracing core units performs an internal ray tracing (Internal RT) operation for a corresponding divided acceleration structure and transmits corresponding ray information to a corresponding ray tracing core unit to perform an external ray tracing (External RT) operation when attempting to access a data node that is not in the corresponding divided acceleration structure in the process of the internal ray tracing operation,
wherein the acceleration structure division processing unit determines a workload rate of each of the plurality of ray tracing core units and divides the acceleration structure based on the workload rate while sharing at least a root data node.
2. The multichip ray tracing device of claim 1 , wherein each of the plurality of ray tracing core units includes a ray tracing core that processes the internal ray tracing operation and a ray output buffer that stores the corresponding ray information in the process of the internal ray tracing operation.
3. The multichip ray tracing device of claim 2 , wherein each of the plurality of ray tracing core units further includes a ray input buffer for storing the corresponding ray information received from the corresponding ray tracing core unit in the process of the external ray tracing operation.
4. The multichip ray tracing device of claim 3 , wherein each of the plurality of ray tracing core units further includes a data transfer unit that reads the corresponding ray information from the ray output buffer and transmits it to the ray input buffer in the corresponding ray tracing core unit for the process of the external ray tracing operation.
5. The multichip ray tracing device of claim 1 , wherein each of the plurality of ray tracing core units is exclusively connected to one of the plurality of memory units and waits to see whether the external ray tracing operation is completed when the corresponding ray information is transmitted to the corresponding ray tracing core unit.
6. The multichip ray tracing device of claim 5 , wherein each of the plurality of ray tracing core units continues the internal ray tracing operation when the external ray tracing operation is completed.
7. A method for multichip ray tracing comprising:
the step of preparing a plurality of memory units;
the step of processing the division of an acceleration structure, wherein the acceleration structure (AS) is divided into a plurality of divided acceleration structures and each of the plurality of divided acceleration structures is stored in a corresponding memory unit among the plurality of memory units; and
the step of ray tracing performed by a plurality of ray tracing core units connected to the plurality of memory units, wherein each of the plurality of ray tracing core units performs an internal ray tracing (Internal RT) operation for a corresponding divided acceleration structure and transmits corresponding ray information to a corresponding ray tracing core unit to perform an external ray tracing (External RT) operation when attempting to access a data node that is not in the corresponding divided acceleration structure in the process of the internal ray tracing operation,
wherein the method further comprises determining a workload rate of each of the plurality of ray tracing core units and dividing the acceleration structure based on the workload rate while sharing at least a root data node.