Granted Patent B2

US 12,635,575 · App. 18/031,592 · Granted May 19, 2026

Inventor: Fabrice Devaux (Lausanne, CH)

Assignee: Qualcomm Incorporated

H10W90/00H10B80/00H10W20/42H10W20/435H10W40/00H10W70/635H10W90/701H10W40/30H10W40/40H10W90/24H10W90/288H10W90/297

Abstract

Claims (43)

1 . A semiconductor device comprising a stack of chips arranged in successive levels along a stacking direction,

wherein:

each of the chips extends in a main plane perpendicular to the stacking direction and comprises:

a first portion extending in the main plane;

a second portion extending in the main plane; and

a stacking surface extending over only the second portion;

the first portion of each of the chips is configured to release more heat during operation than the second portion;

the stacking surface is in mechanical contact with a chip in an adjacent level of the stack;

the first portion of each of the chips comprises a projecting part configured to be exposed to a cooling fluid; and

the second portion of each of the chips of the stack comprises:

a plurality of groups of feed-through vias connected to the first portion and to the second portion and arranged on a first circle; and

a plurality of groups of logic signal through vias arranged along a second circle having a same center as the first circle,

wherein:

one group of the plurality of groups of logic signal through vias is electrically connected to a first circuit and to a second circuit different from the first circuit; and

other groups of the plurality of groups of logic signal through vias are electrically connected to neither of the first circuit and the second circuit.

2 . The semiconductor device of claim 1 , comprising an interconnection substrate, the interconnection substrate having a first face on which the stack is arranged and a second face, opposite the first, provided with connection pins.

3 . The semiconductor device of claim 1 , wherein:

the chips of the stack are provided with through vias;

the through vias of a chip are in electrical contact with the through vias of the chips arranged in adjacent levels; and

the stack of through vias comprises electrical lines of a bus.

4 . The semiconductor device of claim 3 , wherein the stack comprises a buffer chip comprising buffer circuits respectively associated with the electrical lines of the bus.

5 . The semiconductor device of claim 1 , wherein the stack is arranged in a housing of a protective element.

6 . The semiconductor device of claim 1 , wherein a level of the stack comprises at least two chips.

7 . The semiconductor device of claim 1 , wherein:

each of the chips comprises an active face and a passive face opposite the active face; and

two of the chips arranged in adjacent levels of the stack are assembled with their passive faces against each other or with their active faces against each other.

8 . The semiconductor device of claim 1 , wherein the first portion of each of the chips comprises the first circuit and the second portion of each of the chips comprises the second circuit.

9 . The semiconductor device of claim 8 , wherein the first circuit is a processor and the second circuit is a memory array.

10 . The semiconductor device of claim 1 , wherein two of the chips arranged in adjacent levels of the stack are angularly offset by an angle of one of 90°, 180° and 270°.

11 . A semiconductor chip extending in a main plane, the semiconductor chip comprising:

a first portion extending in the main plane and comprising a first circuit; and

a second portion extending in the main plane and comprising a second circuit,

wherein:

the first portion is configured to release more heat than the second portion when the semiconductor chip is operating; and

the second portion also comprises:

a plurality of groups of feed-through vias connected to the first circuit and the second circuit and arranged on a first circle;

a plurality of groups of logic signal through vias arranged along a second circle having a same center as the first circle;

wherein:

one group of the plurality of groups of logic signal through vias is connected to the first circuit and to the second circuit; and

other groups of the plurality of groups of logic signal through vias are connected to neither of the first circuit and the second circuit.

12 . The semiconductor chip of claim 11 , wherein the first circle and the second circle have different radii.

13 . The semiconductor chip of claim 11 , wherein the first circuit is a processor and the second circuit is a memory array.

14 . The semiconductor chip of claim 11 , comprising at least one temperature sensor.

Assignments (2)

Priority Claims (1)

Continuity (1)

References Cited (21)