Granted Patent B2

US 12,499,219 · App. 18/034,051 · Granted Dec 16, 2025

Inventors: Xiangye Wei (Beijing, CN); Liming Xiu (Beijing, CN)

Assignee: Beijing BOE Technology Development Co., Ltd.

G06F21/552G06F2221/034

Abstract

Claims (51)

1 . A security protection method for a heterogeneous system, wherein

the heterogeneous system comprises a processor, wherein the processor comprises a first region, the first region comprising a physical unclonable function circuit; and

the method comprises:

detecting whether an input of the heterogeneous system is abnormal;

acquiring a configuration file in response to the input of the heterogeneous system being detected as abnormal, wherein the acquired configuration file is different from a configuration file of the physical unclonable function circuit that has run; and

reconstructing, on the processor, a mapping of the physical unclonable function circuit based on the acquired configuration file;

wherein the physical unclonable function circuit is a time-average-frequency direct period synthesis physical unclonable function circuit; and

the mapping is constructed by the time-average-frequency direct period synthesis physical unclonable function circuit according to following steps:

generating corresponding characteristic bit streams by extracting first parameters by a first time-average-frequency direct period synthesizer and a second time-average-frequency direct period synthesizer that are symmetrical, wherein the first parameters indicate process deviations of the circuit; and

constructing the mapping by outputting responses by comparing delay features of the characteristic bit streams output by the first time-average-frequency direct period synthesizer and the second time-average-frequency direct period synthesizer.

2 . The security protection method according to claim 1 , wherein reconstructing, on the processor, the mapping of the physical unclonable function circuit based on the acquired configuration file comprises:

based on the acquired configuration file, compiling the physical unclonable function circuit and redesigning the compiled physical unclonable function circuit; and

reconstructing the mapping of the physical unclonable function circuit by storing a result of the redesigned physical unclonable function circuit to the processor.

3 . The security protection method according to claim 2 , wherein reconstructing the mapping of the physical unclonable function circuit by storing the result of the redesigned physical unclonable function circuit to the processor comprises:

reconstructing the mapping of the physical unclonable function circuit by storing the result of the redesigned physical unclonable function circuit to the first region of the processor or a second region, different from the first region, of the processor.

4 . The security protection method according to claim 1 , wherein acquiring the configuration file in response to the input of the heterogeneous system being detected as abnormal comprises:

acquiring a pre-stored configuration file, wherein the acquired pre-stored configuration file is different from the configuration file of the physical unclonable function circuit that has run; or

regenerating a configuration file, wherein the regenerated configuration file is different from the configuration file of the physical unclonable function circuit that has run.

5 . A non-volatile computer-readable storage medium, storing one or more security protection programs for a heterogeneous system, wherein the one or more security protection programs, when loaded and run by a processor, cause the processor to perform the security protection method for the heterogeneous system as defined in claim 1 .

6 . An electronic device, comprising: a memory, a processor, and one or more security protection programs for a heterogeneous system that are stored in the memory and runnable on the processor; wherein the one or more security protection programs, when loaded and run by the processor, cause the processor to perform a security protection method for the heterogeneous system, wherein

the heterogeneous system comprises a processor, wherein the processor comprises a first region, the first region comprising a physical unclonable function circuit; and

wherein the one or more security protection programs, when loaded and run by the processor, cause the processor to perform:

detecting whether an input of the heterogeneous system is abnormal;

acquiring a configuration file in response to the input of the heterogeneous system being detected as abnormal, wherein the acquired configuration file is different from a configuration file of the physical unclonable function circuit that has run; and

reconstructing, on the processor, a mapping of the physical unclonable function circuit based on the acquired configuration file;

wherein the physical unclonable function circuit is a time-average-frequency direct period synthesis physical unclonable function circuit; and

the mapping is constructed by the time-average-frequency direct period synthesis physical unclonable function circuit according to following steps:

generating corresponding characteristic bit streams by extracting first parameters by a first time-average-frequency direct period synthesizer and a second time-average-frequency direct period synthesizer that are symmetrical, wherein the first parameters indicate process deviations of the circuit; and

constructing the mapping by outputting responses by comparing delay features of the characteristic bit streams output by the first time-average-frequency direct period synthesizer and the second time-average-frequency direct period synthesizer.

7 . A processor, comprising:

a programmable logic portion, wherein the programmable logic portion comprises a first region, the first region comprising a physical unclonable function circuit;

a detector, configured to detect whether the processor is attacked; and

an operating portion, configured to acquire a configuration file in response to the processor being attacked and reconstruct, on the programmable logic portion, a mapping of the physical unclonable function circuit based on the acquired configuration file, wherein the acquired configuration file is different from a configuration file of the physical unclonable function circuit that has run;

wherein the physical unclonable function circuit is a time-average-frequency direct period synthesis physical unclonable function circuit; and

the time-averaged-frequency direct period synthesis physical unclonable function circuit comprises:

a first time-average-frequency direct period synthesizer and a second time-average-frequency direct period synthesizer that are symmetrical, wherein the first time-average-frequency direct period synthesizer and the second time-average-frequency direct period synthesizer are configured to generate corresponding characteristic bit streams by extracting first parameters, wherein the first parameters indicate process deviations of the circuit; and

a flip-flop, configured to construct the mapping by outputting responses by comparing delay features of the characteristic bit streams output by the first time-average-frequency direct period synthesizer and the second time-average-frequency direct period synthesizer.

8 . The processor according to claim 7 , wherein the operating portion is further configured to:

based on the acquired configuration file, compile the physical unclonable function circuit and redesign the compiled physical unclonable function circuit; and

reconstruct the mapping of the physical unclonable function circuit by storing a result of the redesigned physical unclonable function circuit to the programmable logic portion.

9 . The processor according to claim 8 , wherein the operating portion is further configured to reconstruct the mapping of the physical unclonable function circuit by storing the result of the redesigned physical unclonable function circuit to the first region of the programmable logic portion or a second region, different from the first region, of the programmable logic portion.

10 . The processor according to claim 7 , wherein the acquired configuration file is a pre-stored configuration file, wherein the pre-stored configuration file is different from the configuration file of the physical unclonable function circuit that has run.

11 . The processor according to claim 7 , wherein the acquired configuration file is a regenerated configuration file, wherein the regenerated configuration file is different from the configuration file of the physical unclonable function circuit that has run.

12 . The electronic device according to claim 6 , wherein the one or more security protection programs, when loaded and run by the processor, cause the processor to perform:

based on the acquired configuration file, compiling the physical unclonable function circuit and redesigning the compiled physical unclonable function circuit; and

reconstructing the mapping of the physical unclonable function circuit by storing a result of the redesigned physical unclonable function circuit to the processor.

13 . The electronic device according to claim 12 , wherein the one or more security protection programs, when loaded and run by the processor, cause the processor to perform:

reconstructing the mapping of the physical unclonable function circuit by storing the result of the redesigned physical unclonable function circuit to the first region of the processor or a second region, different from the first region, of the processor.

14 . The electronic device according to claim 6 , wherein the one or more security protection programs, when loaded and run by the processor, cause the processor to perform:

acquiring a pre-stored configuration file, wherein the acquired pre-stored configuration file is different from the configuration file of the physical unclonable function circuit that has run; or

regenerating a configuration file, wherein the regenerated configuration file is different from the configuration file of the physical unclonable function circuit that has run.

Assignments (2)

Continuity (1)

References Cited (23)