Granted Patent B2

US 12,578,716 · App. 18/034,410 · Granted Mar 17, 2026

Inventor: Luiz Cheim (Raleigh, NC)

Assignee: HITACHI ENERGY LTD

G05B23/0248G05B23/0275

Abstract

Claims (51)

1 . A method comprising:

adjusting, by a processor circuit, at least one probability value associated with a state of at least one component of a first electrical equipment for a subset of nodes of a first plurality of interconnected nodes of a configurable fault tree structure representing at least one failure mode relating to the at least one component of the first electrical equipment, the adjusting based on at least one of a detected state of the at least one component of the first electrical equipment and observed faults in a plurality of electrical equipment;

generating, by the processor circuit, an indication of the state of the at least one component of the first electrical equipment based on the at least one adjusted probability value; and

adjusting, by the processor circuit, an operational state of at least one component of the first electrical equipment based at least in part on the indication.

2 . The method of claim 1 , further comprising configuring the configurable fault tree structure to represent failure modes of the first electrical equipment with a second plurality of interconnected nodes.

3 . The method of claim 2 , wherein configuring the configurable fault tree structure further comprises:

adding, by the processor circuit, an additional node to the first plurality of interconnected nodes;

determining, by the processor circuit, an additional probability value for the additional node associated with a state of at least one component of the first electrical equipment; and

adjusting, by the processor circuit, the at least one adjusted probability value based at least in part on the determined additional probability value.

4 . The method of claim 2 , wherein configuring the configurable fault tree structure further comprises:

removing, by the processor circuit, at least one node from the first plurality of interconnected nodes; and

adjusting, by the processor circuit, the at least one adjusted probability value based at least in part on removing the at least one node from the first plurality of interconnected nodes.

5 . The method of claim 1 , further comprising:

generating, by the processor circuit before adjusting the at least one probability value, the at least one probability value for the subset of nodes based on at least one probability value associated with at least one other node of the first plurality of interconnected nodes.

6 . The method of claim 1 , further comprising:

determining, by the processor circuit, whether the at least one adjusted probability value meets a predetermined probability threshold, wherein generating the indication is further based on the at least one adjusted probability value meeting the predetermined probability threshold.

7 . The method of claim 1 , further comprising:

detecting, by the processor circuit, an updated state of at least one component of the first electrical equipment; and

adjusting, by the processor circuit, the at least one adjusted probability value based at least in part on the detected updated state.

8 . The method of claim 7 , further comprising:

generating, by the processor circuit in response to the at least one further adjusted probability value, an updated indication of the updated state of the at least one component of the first electrical equipment.

9 . The method of claim 1 , wherein adjusting the probability value further comprises:

adjusting a first probability value for a first node of the first plurality of interconnected nodes based at least in part on a received second probability value for a second node of the first plurality of interconnected nodes; and

adjusting the second probability value for the second node based at least in part on the adjusted first probability value for the first node.

10 . The method of claim 1 , further comprising:

receiving, by a system comprising the processor circuit and a memory storing the fault tree structure, a first message from the first electrical equipment indicative of the state of the at least one component of the first electrical equipment; and

transmitting, by the system, a second message comprising the indication to the first electrical equipment.

11 . The method of claim 1 , further comprising:

receiving, by a system comprising the processor circuit and a memory storing the fault tree structure, a first message from the first electrical equipment indicative of a state of the at least one component of the first electrical equipment, wherein adjusting the probability value is further based at least in part on the first message;

receiving, by the system, a second message from a second electrical equipment indicative of a state of a second component of the second electrical equipment; and

adjusting, by the processor circuit, a second probability value associated with the state of the second component based at least in part on the second message.

12 . A system comprising:

a processor circuit; and

a memory comprising machine readable instructions that, when executed by the processor circuit, cause the processor circuit to:

adjust at least one probability value associated with a state of at least one component of a first electrical equipment for a subset of nodes of a first plurality of interconnected nodes of a configurable fault tree structure representing at least one failure mode relating to the at least one component of the first electrical equipment, the adjusting based on at least one of a detected state of the at least one component of the first electrical equipment and observed faults in a plurality of electrical equipment;

generate an indication of the state of the at least one component of the first electrical equipment based on the at least one adjusted probability value; and

adjust an operational state of at least one component of the first electrical equipment based at least in part on the indication.

13 . The system of claim 12 , wherein the memory further comprises the fault tree structure.

14 . The system of claim 12 , wherein the machine readable instructions further cause the processor circuit to:

configure the configurable fault tree structure to represent failure modes of the first electrical equipment with a second plurality of interconnected nodes.

15 . The system of claim 12 , wherein the machine readable instructions further cause the processor circuit to:

generate, before adjusting the probability value, the probability value for the subset of nodes based on at least one probability value associated with at least one other node of the first plurality of interconnected nodes.

16 . The system of claim 12 , wherein the machine readable instructions further cause the processor circuit to:

determine whether the at least one adjusted probability value meets a predetermined probability threshold, wherein generating the indication is further based on the at least one adjusted probability value meeting the predetermined probability threshold.

17 . A non-transitory computer readable medium comprising instructions that, when executed by a processor circuit, cause the processor circuit to:

adjust at least one probability value associated with a state of at least one component of a first electrical equipment for a subset of nodes of a first plurality of interconnected nodes of a configurable fault tree structure representing at least one failure mode relating to the at least one component of the first electrical equipment, the adjusting based on at least one of a detected state of the at least one component of the first electrical equipment and observed faults in a plurality of electrical equipment;

generate an indication of the state of the at least one component of the first electrical equipment based on the at least one adjusted probability value; and

adjust an operational state of at least one component of the first electrical equipment based at least in part on the indication.

18 . The computer readable medium of claim 17 , further comprising the fault tree structure.

19 . The computer readable medium of claim 17 , wherein the instructions further cause the processor circuit to:

configure the configurable fault tree structure to represent failure modes of the first electrical equipment with a second plurality of interconnected nodes.

Assignments (3)

Continuity (2)

References Cited (19)