Granted Patent B2

US 12,501,840 · App. 18/038,382 · Granted Dec 16, 2025

Inventor: George E.G. Sterling (Vancouver, CA)

Assignee: D-WAVE SYSTEMS

H10N60/805G06N10/40H10D1/682H10D1/692H10N60/12H10N69/00

Abstract

Claims (36)

1 . A superconducting integrated circuit comprising:

a tunable parallel-plate capacitor, the tunable parallel-plate capacitor comprising:

a first capacitor plate having a plane;

a second capacitor plate having a plane, the plane of the second capacitor plate geometrically parallel to the plane of the first capacitor plate, wherein the first and second capacitor plate comprise a superconducting material having a high penetration depth; and

a dielectric interposed between the first capacitor plate and the second capacitor plate; and

a magnetic field generator operable to apply a magnetic field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor.

2 . The superconducting integrated circuit of claim 1 , wherein the magnetic field generator comprises a loop of superconducting material overlying the first capacitor plate and the second capacitor plate, a plane of the loop of superconducting material geometrically parallel to the plane of the first capacitor plate and the plane of the second capacitor plate, wherein, in operation, the loop of superconducting material is driven by a current to generate a magnetic field, the magnetic field which tunes a capacitance of the tunable parallel-plate capacitor.

3 . The superconducting integrated circuit of claim 2 , further comprising an interface which, in operation, applies a flux bias to the loop of superconducting material to cause magnetic flux to be introduced into the loop.

4 . The superconducting integrated circuit of claim 1 , wherein the superconducting material is a superconducting metal.

5 . The superconducting integrated circuit of claim 4 , wherein the superconducting metal is at least one of niobium and aluminum.

6 . The superconducting integrated circuit of claim 1 , wherein the superconducting material having a high penetration depth is one of titanium nitride (TiN), niobium titanium nitride (NbTiN), niobium nitride (NbN), and tungsten silicide (WSi).

7 . The superconducting integrated circuit of claim 1 , wherein the dielectric includes a layer of low-loss dielectric.

8 . The superconducting integrated circuit of claim 7 , wherein the low-loss dielectric is at least one of amorphous silicon, crystalline silicon, silicon dioxide, silicon nitride, or amorphous silicon hydride.

9 . The superconducting integrated circuit of claim 1 , further comprising:

a base electrode electrically communicatively coupled to the first capacitor plate; and

a counter electrode electrically communicatively coupled to the second capacitor plate.

10 . A superconducting integrated circuit comprising:

a tunable parallel-plate capacitor, the tunable parallel-plate capacitor comprising:

a first capacitor plate having a plane;

a second capacitor plate having a plane, the plane of the second capacitor plate geometrically parallel to the plane of the first capacitor plate, the second capacitor plate spaced apart from the first capacitor plate, wherein the first and second capacitor plate comprise a superconducting material having a high penetration depth; and

a dielectric interposed between the first capacitor plate and the second capacitor plate; and

an electric field generator operable to apply an electric field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor.

11 . The superconducting integrated circuit of claim 10 , wherein the electric field generator comprises:

a first bias electrode having a plane; and

a second bias electrode having a plane, the plane of the second bias electrode geometrically parallel to the plane of the first bias electrode, the planes of the first and the second bias electrodes orthogonal to the planes of the first and the second capacitor plates, the first and the second bias electrodes situated between the first and the second capacitor plates, and on either side of the dielectric, wherein, in operation, the first and the second bias electrodes provide a bias current to generate an electric field, the electric field which tunes a capacitance of the tunable parallel-plate capacitor.

12 . The superconducting integrated circuit of claim 11 , wherein the bias current includes a direct current (DC) bias current.

13 . The superconducting integrated circuit of claim 11 , wherein the bias current includes an alternating (AC) bias current.

14 . The superconducting integrated circuit of claim 10 , wherein the electric field generator comprises an interdigitated capacitor interposed between the first and the second capacitor plates.

15 . The superconducting integrated circuit of claim 10 , wherein the electric field reduces a capacitance of the tunable parallel-plate capacitor.

16 . The superconducting integrated circuit of claim 10 , wherein the electric field monotonically reduces a capacitance of the tunable parallel-plate capacitor.

17 . The superconducting integrated circuit of claim 10 , wherein the superconducting material is a superconducting metal selected from a group consisting of: niobium and aluminum.

18 . The superconducting integrated circuit of claim 10 , wherein the superconducting material having a high penetration depth is one of titanium nitride (TiN), niobium nitride (NbN), niobium titanium nitride (NbTiN), and tungsten silicide (WSi).

19 . The superconducting integrated circuit of claim 10 , wherein the dielectric includes a layer of low-loss dielectric selected from a group consisting of: amorphous silicon, crystalline silicon, silicon dioxide, silicon nitride, and amorphous silicon hydride.

20 . The superconducting integrated circuit of claim 10 , further comprising:

a base electrode electrically communicatively coupled to the first capacitor plate; and

a counter electrode electrically communicatively coupled to the second capacitor plate.

Assignments (2)

Continuity (2)

References Cited (323)