Granted Patent B2

US 12,501,668 · App. 18/039,920 · Granted Dec 16, 2025

Inventors: Marco Bellini (Zürich, CH); Lars Knoll (Hägglingen, CH); Gianpaolo Romano (Baden, CH); Yulieth Arango (Zürich, CH)

Assignee: HITACHI ENERGY LTD

H10D62/111H01L21/046H10D12/031H10D12/441H10D30/66H10D62/393H10D62/8325

Abstract

Claims (36)

1 . A power semiconductor device comprising:

an electrode;

a base layer of a first conductivity type provided on the electrode;

at least one contact layer provided on the base layer;

a gate contact provided on the base layer and on the at least one contact layer;

an insulation layer between the gate contact and the base layer and between the at least one contact layer and the gate contact, and

at least one zone of a second conductivity type different from the first conductivity type within the base layer,

wherein the at least one contact layer is arranged on a top surface of the base layer, facing away from the electrode,

wherein the at least one contact layer is a metallic layer,

wherein an interface between the metallic layer and the base layer forms a Schottky contact,

wherein the at least one zone is embedded within the base layer such that an outer surface of the zone is completely covered by the base layer and such that the at least one zone is completely enclosed by the base layer in a three-dimensional manner,

wherein the at least one zone is provided centred in lateral directions with respect to the gate contact and a distance between the at least one zone and the insulation layer is at most 1 μm,

wherein the at least one zone comprises a peak doping concentration being at least 10 15 l/cm 3 and at most 5×10 17 l/cm 3 , and

wherein the at least one zone shifts away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

2 . The power semiconductor device according to claim 1 , wherein the base layer comprises a plain top surface and the at least one metallic layer does not extend into the base layer in vertical direction, or the base layer comprises at least one recessed top surface and the at least one contact layer is provided on the at least one recessed top surface.

3 . The power semiconductor device according to claim 1 , wherein at least one of the gate contact and the insulation layer partially overlaps with the at least one contact layer in lateral directions.

4 . The power semiconductor device according to claim 1 , wherein an overlap of the at least one of the gate contact and the insulation layer in lateral directions with the at least one contact layer is at least 0.001 μm and at most 3 μm.

5 . The power semiconductor device according to claim 1 , wherein the at least one zone has a main extension direction in lateral directions transverse to a main extension direction of the base layer in lateral directions.

6 . The power semiconductor device according to claim 5 , wherein the at least one zone has a length in lateral directions being equal to a length of the at least one contact layer.

7 . The power semiconductor device according to claim 1 , wherein the at least one zone comprises a peak doping concentration being one to hundred times higher than a peak doping concentration of the base layer.

8 . The power semiconductor device according to claim 1 , wherein a thickness of the at least one zone is at least 0.1 μm and at most 1 μm.

9 . The power semiconductor device according to claim 1 , wherein the at least one zone has a width in lateral directions along a main extension direction of the base layer, which is less than 40% of a length of the gate contact in lateral directions along the main extension direction of the base layer.

10 . A method for producing a power semiconductor device comprising:

providing an electrode;

providing a base layer of a first conductivity type on the electrode;

applying at least one contact layer on the base layer;

applying a gate contact and an insulation layer on the base layer and at least one contact layer,

wherein the insulation layer is applied between the gate contact and the base layer and between the at least one contact layer and the gate contact, and

generating at least one zone of a second conductivity type within the base layer,

wherein the at least one contact layer is arranged on a top surface of the base layer, facing away from the electrode,

wherein the at least one contact layer is a metallic layer,

wherein an interface between the metallic layer and the base layer forms a Schottky contact,

wherein the at least one zone is embedded within the base layer such that an outer surface of the zone is completely covered by the base layer and such that the at least one zone is completely enclosed by the base layer in a three-dimensional manner,

wherein the at least one zone is provided centred in lateral directions with respect to the gate contact and a distance between the at least one zone and the insulation layer is at most 1 μm,

wherein the at least one zone comprises a peak doping concentration being at least 10 15 l/cm 3 and at most 5×10 17 l/cm 3 , and

the at least one zone shifts away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

Assignments (3)

Priority Claims (1)

Continuity (1)

References Cited (9)