Electret capsule
The present invention relates generally to the field of electret capsule, and more particularly to a circuit configuration of an impedance converter integrated in an electret capsule such as for use in condenser microphones. The electret capsule of a microphone may include a gate biasing field effect transistor (FET) to facilitate biasing of a low noise FET. Advantageously, the use of low noise FET in the electret capsule of a microphone provides for a reduced cost, while achieving lower self-noise.
1. An electret capsule comprising:
a biasing arrangement of two or more field effect transistors (FETs), each FET including a source electrode, a drain electrode, and a gate electrode;
a backplate assembly including a backplate, an acoustic housing, one or more damping discs, and a contact spring;
a diaphragm assembly coupled to said backplate assembly via a gasket; and
an external housing including a protection mesh;
wherein the biasing arrangement comprises the source electrode of at least a first FET of the two or more FETs being in electrical connection with the source electrode of at least a second FET of the two or more FETs, said first FET being an impedance converter low noise FET, said second FET being a gate biasing FET including an open drain configuration and configured to facilitate biasing said first FET.
2. The electret capsule of claim 1 , wherein said backplate is connected to a printed circuit board (PCB) via the contact spring.
3. The electret capsule of claim 1 , further comprising a connector, wherein said connector is at least one of a PCB pin, a wire lead, and a terminal.
4. The electret capsule of claim 1 , further comprising biasing diodes configured to reduce noise and signal gain, said diodes connected in series and arranged to connect said first FET and said second FET to ground to facilitate a positive bias potential.
5. The electret capsule of claim 4 , wherein said biasing diodes are at least one of a zener diode and a schottky diode.
6. The electret capsule of claim 1 , further comprising a biasing resistor including a first terminal connected in series to said source electrode of said first FET and a second terminal connected to ground.
7. The electret capsule of claim 6 , wherein said resistor has a resistance value of about 1KΩ to facilitate compensating for variations in output characteristics of said two or more FETs.
8. The electret capsule of claim 1 , further comprising a noise rejection configuration for an output signal, said configuration including an inductor having a first terminal connected in series to said drain electrode of said first FET and a second terminal in series with a first capacitor and a second capacitor.