Chip, system of noise analysis and method of noise analysis
A chip comprises a plurality of signal receiving circuits, a transceiver circuit and a memory circuit. The plurality of signal receiving circuits are set at different locations on the chip. The transceiver circuit includes a dynamic switch circuit and a baseband processor. The dynamic switch circuit is configured to output a to-be-analyzed signal from the one of the plurality of signal receiving circuits. The baseband processor is configured to obtain a frequency spectrum and magnitude of the to-be-analyzed signal, and obtain a data packet of an input radio-frequency signal received by an external antenna. The memory circuit is configured to store the frequency spectrum and magnitude of the to-be-analyzed signal, and transmit the frequency spectrum and magnitude to an external computing device, so as to determine an interference path, an interference source or a combination thereof of an interference signal of the transceiver circuit through the external computing device.
1. A chip, comprising:
a plurality of signal receiving circuits, set at different locations on the chip;
a transceiver circuit, comprising:
a dynamic switch circuit, configured to output a to-be-analyzed signal from the one of the plurality of signal receiving circuits; and
a baseband processor, configured to obtain a frequency spectrum and magnitude of the to-be-analyzed signal, and configured to obtain a data packet of an input radio-frequency signal received by an external antenna; and
a memory circuit, configured to store the frequency spectrum and magnitude of the to-be-analyzed signal of each of the plurality of signal receiving circuits, and transmit the frequency spectrum and magnitude of the to-be-analyzed signal of each of the plurality of signal receiving circuits to an external computing device, so as to determine an interference path, an interference source or a combination thereof of an interference signal of the transceiver circuit through the external computing device.
2. The chip of claim 1 , wherein the dynamic switch circuit is configured to output the one of the to-be-analyzed signal and the input radio-frequency signal, and the transceiver circuit further comprises:
a receiving processor, coupled between the dynamic switch circuit and the baseband processor, configured to demodulate the to-be-analyzed signal to generate a to-be-analyzed baseband signal, and configured to demodulate the input radio-frequency signal to generate a input baseband signal,
wherein the baseband processor is configured to obtain the frequency spectrum and magnitude of the to-be-analyzed signal from the to-be-analyzed baseband signal, and obtain the data packet from the input baseband signal.
3. The chip of claim 1 , wherein the plurality of signal receiving circuits include a plurality of first signal receiving circuits, wherein the chip is configured to be set on a first surface of an exposed pad, and the plurality of first signal receiving circuits are configured to transmit a plurality of first signals from different locations on the exposed pad to the transceiver circuit.
4. The chip of claim 1 , further comprising a substrate, a plurality of functional blocks or a combination thereof,
wherein the plurality of signal receiving circuits include a plurality of second signal receiving circuits, the plurality of second signal receiving circuits are configured to transmit a plurality of second signals to the transceiver circuit,
wherein the plurality of second signals are sourced from different locations of the substrate, or sourced from different functional blocks among the plurality of functional blocks.
5. The chip of claim 1 , further comprising:
a plurality of input-output pins,
wherein the plurality of signal receiving circuits include a plurality of third signal receiving circuits, the plurality of third signal receiving circuits are configured to transmit a plurality of third signals from the plurality of input-output pins to the transceiver circuit.
6. The chip of claim 1 , wherein the dynamic switch circuit is configured to output a plurality of signals respectively received by the plurality of signal receiving circuits sequentially as the to-be-analyzed signal.
7. The chip of claim 1 , wherein the plurality of signal receiving circuits include a metal wire, an antenna unit or a combination thereof.
8. A method of noise analysis, suitable for a system of noise analysis, wherein the system of noise analysis includes a chip and an external computing device, and the chip includes a plurality of signal receiving circuits, a transceiver circuit and a memory circuit, the method of noise analysis comprises:
controlling a dynamic switch circuit of the transceiver circuit to output a to-be-analyzed signal from the one of the plurality of signal receiving circuits;
controlling a baseband processor of the transceiver circuit to obtain a frequency spectrum and magnitude of the to-be-analyzed signal of each of the plurality of signal receiving circuits, wherein the baseband processor is configured to obtain a data packet of an input radio-frequency signal received by an external antenna;
storing the frequency spectrum and magnitude of the to-be-analyzed signal of each of the plurality of signal receiving circuits to the memory circuit; and
generating a display signal correspondingly according to the frequency spectrum and magnitude of the to-be-analyzed signal of each of the plurality of signal receiving circuits through the external computing device, wherein the display signal is configured to control a display device to generate a display image, so as to determine an interference path, an interference source or a combination thereof of an interference signal of the transceiver circuit.
9. The method of claim 8 , wherein controlling the baseband processor of the transceiver circuit to obtain the frequency spectrum and magnitude of the to-be-analyzed signal of each of the plurality of signal receiving circuits comprises:
demodulating the to-be-analyzed signal to generate a to-be-analyzed baseband signal through a receiving processor of the transceiver circuit; and
obtaining the frequency spectrum and magnitude of the to-be-analyzed signal from the to-be-analyzed baseband signal through the baseband processor of the transceiver circuit.
10. The method of claim 8 , wherein the plurality of signal receiving circuits include a plurality of first signal receiving circuits, wherein the chip is set on a first surface of an exposed pad, and the plurality of first signal receiving circuits are configured to transmit a plurality of first signals from different locations on the exposed pad to the transceiver circuit.
11. The method of claim 8 , wherein the chip includes a substrate, a plurality of functional blocks or a combination thereof, wherein the plurality of signal receiving circuits include a plurality of second signal receiving circuits, the plurality of second signal receiving circuits are configured to transmit a plurality of second signals to the transceiver circuit,
wherein the plurality of second signals are sourced from different locations of the substrate, or sourced from different functional blocks among the plurality of functional blocks.
12. The method of claim 8 , wherein the chip includes a plurality of input-output pins, wherein the plurality of signal receiving circuits include a plurality of third signal receiving circuits, the plurality of third signal receiving circuits are configured to transmit a plurality of third signals from the plurality of input-output pins to the transceiver circuit.
13. The method of claim 8 , wherein controlling the dynamic switch circuit of the transceiver circuit to output the to-be-analyzed signal from the one of the plurality of signal receiving circuits comprises:
receiving a plurality of signals through the plurality of signal receiving circuits, respectively; and
controlling the dynamic switch circuit of the transceiver circuit to output the plurality of signals sequentially as the to-be-analyzed signal.
14. The method of claim 8 , wherein the plurality of signal receiving circuits include a metal wire, an antenna unit or a combination thereof.
15. A system of noise analysis, comprising:
a chip, comprising:
a plurality of signal receiving circuits, set at different locations on the chip;
a transceiver circuit, comprising:
a dynamic switch circuit, configured to output a to-be-analyzed signal from the one of the plurality of signal receiving circuits; and
a baseband processor, configured to obtain a frequency spectrum and magnitude of the to-be-analyzed signal, and configured to obtain a data packet of an input radio-frequency signal received by an external antenna; and
a memory circuit, configured to store the frequency spectrum and magnitude of the to-be-analyzed signal of each of the plurality of signal receiving circuits; and
an external computing device, configured to generate a display signal correspondingly according to the frequency spectrum and magnitude of the to-be-analyzed signal of each of the plurality of signal receiving circuits, wherein the display signal is configured to control a display device to generate a display image, so as to determine an interference path, an interference source or a combination thereof of an interference signal of the transceiver circuit.
16. The system of claim 15 , wherein the dynamic switch circuit is configured to output one of the to-be-analyzed signal and the input radio-frequency signal, and the transceiver circuit further comprises:
a receiving processor, coupled between the dynamic switch circuit and the baseband processor, configured to demodulate the to-be-analyzed signal to generate a to-be-analyzed baseband signal, and configured to demodulate the input radio-frequency signal to generate a input baseband signal,
wherein the baseband processor is configured to obtain the frequency spectrum and magnitude of the to-be-analyzed signal from the to-be-analyzed baseband signal, and obtain the data packet from the input baseband signal.
17. The system of claim 15 , wherein the plurality of signal receiving circuits include a plurality of first signal receiving circuits, wherein the chip is configured to be set on a first surface of an exposed pad, and the plurality of first signal receiving circuits are configured to transmit a plurality of first signals from different locations on the exposed pad to the transceiver circuit.
18. The system of claim 15 , wherein the chip further comprises a substrate, a plurality of functional blocks or a combination thereof,
wherein the plurality of signal receiving circuits include a plurality of second signal receiving circuits, the plurality of second signal receiving circuits are configured to transmit a plurality of second signals to the transceiver circuit,
wherein the plurality of second signals are sourced from different locations of the substrate, or sourced from different functional blocks among the plurality of functional blocks.
19. The system of claim 15 , wherein the chip further comprising:
a plurality of input-output pins,
wherein the plurality of signal receiving circuits include a plurality of third signal receiving circuits, the plurality of third signal receiving circuits are configured to transmit a plurality of third signals from the plurality of input-output pins to the transceiver circuit.
20. The system of claim 15 , wherein the plurality of signal receiving circuits include a metal wire, an antenna unit or a combination thereof.