Techniques for neural network execution utilizing memoization
A system and method for reducing power consumption in processing artificial neural networks utilizes memoization techniques. The method includes receiving computer code representing a neural network model, the neural network model including an input layer having a first plurality of nodes, and an output layer having a second plurality of nodes; detecting in the computer code a cacheable block of instructions, the cacheable block of instructions including an input and an output, wherein the input and the output are local to the cacheable block of instructions; determining a first power consumption corresponding to retrieving a value from a value cache; determining a second power consumption corresponding to executing the cacheable block of instructions; and storing in the value cache an input value corresponding to the input and an output value corresponding to the output, in response to determining that the second power consumption is higher than the first power consumption.
1 . A method for reducing power consumption in processing artificial neural networks utilizing memoization, comprising:
receiving computer code representing a neural network model, the neural network model including an input layer having a first plurality of nodes, and an output layer having a second plurality of nodes;
detecting in the computer code a cacheable block of instructions, the cacheable block of instructions including an input and an output, wherein the input and the output are local to the cacheable block of instructions, and wherein the cacheable block of instructions does not call another function for input outside of the cacheable block of instructions;
determining a first power consumption corresponding to retrieving a value from a value cache;
determining a second power consumption corresponding to executing the cacheable block of instructions; and
storing in the value cache an input value corresponding to the input and an output value corresponding to the output, in response to determining that the second power consumption is higher than the first power consumption.
2 . The method of claim 1 , further comprising:
determining a number of least significant bits (LSBs) of the input; and
storing in the value cache a first input value and a second input value, each with a respective output value, wherein the first input value and the second input value differ from each other by a number of LSBs equal to or less than the determined number of LSBs.
3 . The method of claim 2 , wherein the first input value and the second input value are stored in the value cache without the LSBs.
4 . The method of claim 1 , further comprising:
determining a number of LSBs of the output; and
storing in the value cache a first output value and a second output value, each with a respective input value, wherein the first output value and the second output value differ from each other by a number of LSBs equal to or less than the determined number of LSBs.
5 . The method of claim 4 , wherein the first output value and the second output value are stored in the value cache without the LSBs.
6 . The method of claim 1 , further comprising:
determining a frequency which an input value is received as an input to the cacheable block of instructions, and
storing in the value cache an input value corresponding to the input further in response to determining that the frequency is above a predetermined threshold.
7 . The method of claim 1 , further comprising:
evicting a value from the value cache.
8 . The method of claim 1 , wherein the cacheable block of instructions corresponds to a single layer of the neural network.
9 . The method of claim 1 , wherein the cacheable block of instructions corresponds to a first layer of the neural network and a second layer of the neural network, wherein the second layer is consecutive to the first layer.
10 . A non-transitory computer readable medium having stored thereon instructions for causing a processing circuitry to execute a process, the process comprising:
receiving computer code representing a neural network model, the neural network model including an input layer having a first plurality of nodes, and an output layer having a second plurality of nodes;
detecting in the computer code a cacheable block of instructions, the cacheable block of instructions including an input and an output, wherein the input and the output are local to the cacheable block of instructions, and wherein the cacheable block of instructions does not call another function for input outside of the cacheable block of instructions;
determining a first power consumption corresponding to retrieving a value from a value cache;
determining a second power consumption corresponding to executing the cacheable block of instructions; and
storing in the value cache an input value corresponding to the input and an output value corresponding to the output, in response to determining that the second power consumption is higher than the first power consumption.
11 . A system for reducing power consumption in processing artificial neural networks utilizing memoization, comprising:
a processing circuitry; and
a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:
receive computer code representing a neural network model, the neural network model including an input layer having a first plurality of nodes, and an output layer having a second plurality of nodes;
detect in the computer code a cacheable block of instructions, the cacheable block of instructions including an input and an output, wherein the input and the output are local to the cacheable block of instructions, and wherein the cacheable block of instructions does not call another function for input outside of the cacheable block of instructions;
determine a first power consumption corresponding to retrieving a value from a value cache;
determine a second power consumption corresponding to executing the cacheable block of instructions; and
store in the value cache an input value corresponding to the input and an output value corresponding to the output, in response to determining that the second power consumption is higher than the first power consumption.
12 . The system of claim 11 , wherein the memory includes further instructions which when executed by the processing circuitry further configure the system to:
determine a number of least significant bits (LSBs) of the input; and
store in the value cache a first input value and a second input value, each with a respective output value, wherein the first input value and the second input value differ from each other by a number of LSBs equal to or less than the determined number of LSBs.
13 . The system of claim 12 , wherein the memory includes further instructions which when executed by the processing circuitry further configure the system to:
store the first input value and the second input value in the value cache without the LSBs.
14 . The system of claim 11 , wherein the memory includes further instructions which when executed by the processing circuitry further configure the system to:
determine a number of LSBs of the output; and
store in the value cache a first output value and a second output value, each with a respective input value, wherein the first output value and the second output value differ from each other by a number of LSBs equal to or less than the determined number of LSBs.
15 . The system of claim 14 , wherein the memory includes further instructions which when executed by the processing circuitry further configure the system to:
store the first output value and the second output value in the value cache without the LSBs.
16 . The system of claim 11 , wherein the memory includes further instructions which when executed by the processing circuitry further configure the system to:
determine a frequency which an input value is received as an input to the cacheable block of instructions, and;
store in the value cache an input value corresponding to the input further in response to determining that the frequency is above a predetermined threshold.
17 . The system of claim 11 , wherein the memory includes further instructions which when executed by the processing circuitry further configure the system to:
evict a value from the value cache.
18 . The system of claim 11 , wherein the cacheable block of instructions corresponds to a single layer of the neural network.
19 . The system of claim 11 , wherein the cacheable block of instructions corresponds to a first layer of the neural network and a second layer of the neural network, wherein the second layer is consecutive to the first layer.