Techniques for optimizing neural networks for memoization using shifted value localization
A system and method for increasing cache hits in a value cache utilizing memoization is disclosed. The method includes receiving an input matrix for a parallel processing circuitry, wherein the parallel processing circuitry configured to process the input matrix with a second matrix; selecting a portion of the input matrix, wherein the portion includes a plurality of values; adjusting a first value of the plurality of values based on a second value of the plurality of values; generating a new input matrix based on the input matrix and the adjusted first value; and configuring the parallel processing circuitry to process the new input matrix with the second matrix.
1 . A method for increasing cache hits in a value cache utilizing memoization, comprising:
receiving an input matrix for a parallel processing circuitry, wherein the parallel processing circuitry configured to process the input matrix with a second matrix;
selecting a portion of the input matrix, wherein the portion includes a plurality of values;
adjusting a first value of the plurality of values based on a second value of the plurality of values;
generating a new input matrix based on the input matrix and the adjusted first value; and
configuring the parallel processing circuitry to process the new input matrix with the second matrix.
2 . The method of claim 1 , further comprising:
determining a threshold value for comparing the first value to the second value.
3 . The method of claim 2 , further comprising:
adjusting the first value of the plurality of values in response to determining that the second value of the plurality of values is within the determined threshold value from the first value.
4 . The method of claim 2 , further comprising:
determining the threshold value based on a number of least significant bits (LSBs).
5 . The method of claim 1 , further comprising:
adjusting a third value of the plurality of values based on a target function of a neural network.
6 . The method of claim 1 , further comprising:
adjusting the first value of the plurality of values to the second value of the plurality of values.
7 . The method of claim 1 , further comprising:
performing a z-buffer depth test on the plurality of values; and
generating a threshold value for the portion of the input matrix based on a result of the z-buffer depth test.
8 . The method of claim 7 , further comprising:
adjusting the first value of the plurality of values in response to determining that the second value of the plurality of values is within the generated threshold value from the first value.
9 . The method of claim 1 , wherein the input matrix is a kernel of a convolutional neural network (CNN).
10 . The method of claim 1 , wherein the portion overlaps with a second portion, such that a value of the portion is also a value of the second portion.
11 . The method of claim 1 , wherein the second matrix is any one of: a representation of an image, a fully connected layer of a CNN, and a convolutional layer of a CNN.
12 . A non-transitory computer readable medium having stored thereon instructions for causing a processing circuitry to execute a process, the process comprising:
receiving an input matrix for a parallel processing circuitry, wherein the parallel processing circuitry configured to process the input matrix with a second matrix;
selecting a portion of the input matrix, wherein the portion includes a plurality of values;
adjusting a first value of the plurality of values based on a second value of the plurality of values;
generating a new input matrix based on the input matrix and the adjusted first value; and
configuring the parallel processing circuitry to process the new input matrix with the second matrix.
13 . A system for increasing cache hits in a value cache utilizing memoization, comprising:
a processing circuitry; and
a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:
receive an input matrix for a parallel processing circuitry, wherein the parallel processing circuitry configured to process the input matrix with a second matrix;
select a portion of the input matrix, wherein the portion includes a plurality of values;
adjust a first value of the plurality of values based on a second value of the plurality of values;
generate a new input matrix based on the input matrix and the adjusted first value; and
configure the parallel processing circuitry to process the new input matrix with the second matrix.
14 . The system of claim 13 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
determine a threshold value for comparing the first value to the second value.
15 . The system of claim 14 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
adjust the first value of the plurality of values in response to determining that the second value of the plurality of values is within the determined threshold value from the first value.
16 . The system of claim 14 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
determine the threshold value based on a number of least significant bits (LSBs).
17 . The system of claim 13 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
adjust a third value of the plurality of values based on a target function of a neural network.
18 . The system of claim 13 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
adjust the first value of the plurality of values to the second value of the plurality of values.
19 . The system of claim 13 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
perform a z-buffer depth test on the plurality of values; and
generate a threshold value for the portion of the input matrix based on a result of the z-buffer depth test.
20 . The system of claim 19 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
adjust the first value of the plurality of values in response to determining that the second value of the plurality of values is within the generated threshold value from the first value.
21 . The system of claim 13 , wherein the input matrix is a kernel of a convolutional neural network (CNN).
22 . The system of claim 13 , wherein the portion overlaps with a second portion, such that a value of the portion is also a value of the second portion.
23 . The system of claim 13 , wherein the second matrix is any one of: a representation of an image, a fully connected layer of a CNN, and a convolutional layer of a CNN.