Die Design Featuring Application Driven Luminance Distribution

1 . A light emitting diode (LED) device comprising:

a first doped semiconductor layer;

a second doped semiconductor layer;

a plurality of first contacts each electrically connected to the first doped semiconductor layer;

a plurality of edge contacts each electrically connected to the second doped semiconductor layer, the plurality of edge contacts comprising discrete segments separated by an insulating layer; and

an array of a plurality of vias arranged across the device, the plurality of vias connecting the plurality of first contacts to the first doped semiconductor layer, each of the plurality of vias connecting at most one corresponding first contact of the plurality of first contacts to the first doped semiconductor layer.

2 . The device of claim 1 , wherein the insulating layer comprises one or more of silicon nitride (SiN) and silicon oxide (SiO x ).

3 . The device of claim 1 , wherein the insulating layer comprises a bilayer insulating layer.

4 . The device of claim 3 , wherein the bilayer insulating layer comprises silicon nitride (SiN) and silicon oxide (SiO x ).

5 . The device of claim 1 , wherein the plurality of edge contacts comprise aluminum.

6 . The device of claim 1 , wherein the first doped semiconductor layer is between the plurality of first contacts and the second doped semiconductor layer.

7 . The device of claim 6 , further comprising an insulating layer between the first doped semiconductor layer and the plurality of first contacts.

8 . The device of claim 7 , wherein the plurality of vias connected the plurality of first contacts to the first doped semiconductor layer through the insulating layer.

9 . The device of claim 8 , further comprising an electrode layer between the first doped semiconductor layer and the insulating layer and in contact with the first doped semiconductor layer, wherein the electrode layer is substantially transparent.

10 . The device of claim 9 , wherein the electrode layer is arranged as multiple discrete areal segments separated by electrically insulating material so that transverse electrical conduction between adjacent areal segments is substantially prevented, and each areal segment of the electrode layer is connected to at most one corresponding contact of the plurality of first contacts.

11 . The device of claim 1 , wherein the second doped semiconductor layer is between the plurality of first contacts and the first doped semiconductor layer.

12 . The device of claim 11 , further comprising an insulating layer between the second doped semiconductor layer and the plurality of first contacts.

13 . The device of claim 12 , wherein the plurality of vias connect the plurality of first contacts to the first doped semiconductor layer through the insulating layer and the second doped semiconductor layer, and the plurality of vias are electrically insulated from the second doped semiconductor layer.

14 . The device of claim 1 , further comprising an array of a second plurality of vias arranged across the device, the second plurality of vias connecting the plurality of edge contacts to the second doped semiconductor layer.

15 . The device of claim 14 , wherein each via of the second plurality of vias connects at most one corresponding contact of the plurality of edge contacts to the second doped semiconductor layer.

16 . A light emitting diode (LED) device comprising:

an n-doped semiconductor layer;

a p-doped semiconductor layer;

a plurality of first contacts each electrically connected to the p-doped semiconductor layer;

a plurality of edge contacts each electrically connected to the n-doped semiconductor layer, the plurality of edge contacts comprising discrete segments separated by an insulating layer; and

an array of a plurality of vias arranged across the device, the plurality of vias connecting the plurality of first contacts to the p-doped semiconductor layer, each of the plurality of vias connecting at most one corresponding first contact of the plurality of first contacts to the p-doped semiconductor layer.

17 . The device of claim 16 , wherein the insulating layer comprises one or more of silicon nitride (SiN) and silicon oxide (SiO x ).

18 . The device of claim 16 , wherein the insulating layer comprises a bilayer insulating layer.

19 . The device of claim 18 , wherein the bilayer insulating layer comprises silicon nitride (SiN) and silicon oxide (SiO x ).

20 . The device of claim 16 , wherein the plurality of edge contacts comprise aluminum.