Pixel circuit with pulse width compensation and operation method thereof

1. A pixel circuit with pulse width compensation, and the pixel circuit comprising:

a pulse width modulation circuit comprising:

a P-type pulse width compensation transistor; and

a first P-type control transistor electrically connected to the P-type pulse width compensation transistor; and

a pulse amplitude modulation circuit electrically connected to the pulse width modulation circuit, and the pulse amplitude modulation circuit comprising:

a second P-type control transistor electrically connected to the first P-type control transistor, wherein the second P-type control transistor comprises a first terminal;

a first capacitor electrically connected to the second P-type control transistor;

a second capacitor connected in series with the first capacitor. wherein one terminal of the second capacitor is electrically connected to the first terminal of the second P-type control transistor and the first capacitor, and another terminal of the second capacitor receives a reference voltage;

a P-type driving transistor electrically connected to the first capacitor; and

a light-emitting element electrically connected to the P-type driving transistor.

2. The pixel circuit of claim 1 , wherein the first P-type control transistor comprises a control terminal, the P-type pulse width compensation transistor comprises a first terminal, a second terminal and a control terminal, the first terminal of the P-type pulse width compensation transistor is electrically connected to the control terminal of the first P-type control transistor, the second terminal of the P-type pulse width compensation transistor receives a scanning voltage, and the control terminal of the P-type pulse width compensation transistor receives a light-emitting signal.

3. The pixel circuit of claim 1 , wherein the first P-type control transistor comprises a control terminal, and the pulse width modulation circuit comprises:

a data writing transistor comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the data writing transistor is electrically connected to the control terminal of the first P-type control transistor, the second terminal of the data writing transistor receives a data voltage, and the control terminal of the data writing transistor receives a control signal.

4. The pixel circuit of claim 1 , wherein the first P-type control transistor comprises a first terminal, a second terminal and a control terminal, and the pulse width modulation circuit comprises:

a first P-type reset transistor comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the first P-type reset transistor is electrically connected to the first terminal of the first P-type control transistor, the second terminal of the first P-type reset transistor is electrically connected to the control terminal of the first P-type control transistor, and the control terminal of the first P-type reset transistor receives a control signal; and

a second P-type reset transistor comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the second P-type reset transistor is electrically connected to the second terminal of the first P-type control transistor, the second terminal of the second P-type reset transistor receives a reference voltage, and the control terminal of the second P-type reset transistor receives the control signal.

5. The pixel circuit of claim 1 , wherein the first P-type control transistor comprises a first terminal, the second P-type control transistor comprises a control terminal, and the pulse width modulation circuit comprises:

a P-type reset transistor comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the P-type reset transistor is electrically connected to the first terminal of the first P-type control transistor and the control terminal of the second P-type control transistor, the second terminal of the P-type reset transistor receives a reference voltage, and the control terminal of the P-type reset transistor receives an inverted light-emitting signal.

6. The pixel circuit of claim 1 , wherein the second P-type control transistor comprises the first terminal, a second terminal and a control terminal, the second terminal of the second P-type control transistor receives a driving voltage, and the pulse amplitude modulation circuit comprises:

a P-type reset transistor comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the P-type reset transistor is electrically connected to the first terminal of the second P-type control transistor, the second terminal of the P-type reset transistor receives a reference voltage, and the control terminal of the P-type reset transistor receives an inverted light-emitting signal.

7. The pixel circuit of claim 1 , wherein the P-type driving transistor comprises a first terminal, a second terminal and a control terminal, the light-emitting element comprises an anode and a cathode, the anode of the light-emitting element receives a first operating voltage, the cathode of the light-emitting element is electrically connected to the second terminal of the P-type driving transistor, the first terminal of the P-type driving transistor receives a second operating voltage, the control terminal of the P-type driving transistor is electrically connected to the first capacitor, and the first operating voltage is higher than the second operating voltage.

8. The pixel circuit of claim 7 , wherein the pulse amplitude modulation circuit comprises:

a P-type switching transistor comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the P-type switching transistor is electrically connected to the control terminal of the P-type driving transistor, the second terminal of the P-type switching transistor receives the first operating voltage, and the control terminal of the P-type switching transistor receives a control signal.

9. The pixel circuit of claim 1 , wherein the pulse amplitude modulation circuit comprises:

a P-type threshold voltage compensation transistor comprising a first terminal, a second terminal and a control terminal, wherein the second terminal and the control terminal of the P-type threshold voltage compensation transistor receive a reference voltage; and

a P-type switching transistor comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the P-type switching transistor is electrically connected to the first capacitor, the second terminal of the P-type switching transistor is electrically connected to the first terminal of the P-type threshold voltage compensation transistor, and the control terminal of the P-type switching transistor receives a control signal.

10. A pixel circuit with pulse width compensation, and the pixel circuit comprising:

a pulse width modulation circuit comprising:

a P-type pulse width compensation transistor; and

a first P-type control transistor electrically connected to the P-type pulse width compensation transistor; and

a pulse amplitude modulation circuit electrically connected to the pulse width modulation circuit, and the pulse amplitude modulation circuit comprising:

a P-type driving transistor electrically connected to a light-emitting element; and

a second P-type control transistor electrically connected to the first P-type control transistor, and the second P-type control transistor electrically connected to the P-type driving transistor through a capacitor, wherein in an emission period, the P-type pulse width compensation transistor is turned on, so that the first P-type control transistor is turned on to turn on the second P-type control transistor, so as to turn on the P-type driving transistor for driving the light-emitting element to emit light.

11. The pixel circuit of claim 10 , wherein the pulse width modulation circuit comprises a first P-type reset transistor, a second P-type reset transistor and a third P-type reset transistor, the pulse amplitude modulation circuit comprises a fourth P-type reset transistor and a P-type switching transistor, the first P-type control transistor comprises a first terminal, a second terminal and a control terminal, the first terminal of the first P-type control transistor is electrically connected to the first and third P-type reset transistors, the second terminal of the first P-type control transistor is electrically connected to the second P-type reset transistor, the control terminal of the first P-type control transistor is electrically connected between the P-type pulse width compensation transistor and the first P-type reset transistor, the fourth P-type reset transistor is electrically connected to the second P-type control transistor, and the P-type switching transistor is electrically connected to the P-type driving transistor and the light-emitting element, wherein in a reset period, the P-type pulse width compensation transistor is turned off by a disabling level of a light-emitting signal, the third and fourth P-type reset transistors are turned on by an enabling level of an inverted light-emitting signal, and the first and second P-type reset transistors and the P-type switching transistor are turned on by the enabling level of a control signal, so that the P-type driving transistor is turned off.

12. The pixel circuit of claim 10 , wherein the pulse width modulation circuit comprises a data writing transistor, the pulse amplitude modulation circuit comprises a P-type threshold voltage compensation transistor and a P-type switching transistor, the first P-type control transistor comprises a control terminal, the control terminal of the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor and the data writing transistor, the P-type switching transistor is electrically connected to the P-type driving transistor and the capacitor through a node, the P-type threshold voltage compensation transistor is electrically connected to the P-type switching transistor, and the P-type threshold voltage compensation transistor receives a reference voltage, wherein in a compensation and data input period, the P-type pulse width compensation transistor is turned off by a disabling level of a light-emitting signal, the data writing transistor and the P-type switching transistor are turned on by an enabling level of a control signal, so that the data writing transistor writes a data voltage to the control terminal of the first P-type control transistor, and the P-type threshold voltage compensation transistor discharges the node to the reference voltage plus a threshold voltage of the P-type threshold voltage compensation transistor.

13. The pixel circuit of claim 12 , wherein the first P-type control transistor further comprises a first terminal, the second P-type control transistor comprises a first terminal, a second terminal and a control terminal, the P-type driving transistor comprises a control terminal, the control terminal of the first P-type control transistor is electrically connected to the data writing transistor, the first terminal of the first P-type control transistor is electrically connected to the control terminal of the second P-type control transistor, and the first terminal of the second P-type control transistor is electrically connected to the control terminal of the P-type driving transistor through the capacitor, wherein in the emission period, the P-type pulse width compensation transistor is turned on by the enabling level of the light-emitting signal, when the data voltage is greater than a sawtooth voltage received by the P-type pulse width compensation transistor, the first P-type control transistor is turned on to turn on the second P-type control transistor, and the second terminal of the second P-type control transistor receives a driving voltage having the enabling level, so that the P-type driving transistor is turned on to drive the light-emitting element to emit the light.

14. The pixel circuit of claim 10 , wherein the pulse width modulation circuit comprises a P-type reset transistor, the pulse amplitude modulation circuit comprises a P-type reset transistor, the P-type reset transistor of the pulse width modulation circuit is electrically connected to the first P-type control transistor, and the P-type reset transistor of the pulse amplitude modulation circuit is electrically connected to the second P-type control transistor, wherein in a turn-off period, the P-type pulse width compensation transistor is turned off by a disabling level of a light-emitting signal, and the P-type reset transistor of the pulse width modulation circuit and the P-type reset transistor of the pulse amplitude modulation circuit are turned on by an enabling level of an inverted light-emitting signal.

15. An operation method of a pixel circuit with pulse width compensation, the pixel circuit comprising a pulse width modulation circuit and a pulse amplitude modulation circuit, the pulse width modulation circuit comprising a P-type pulse width compensation transistor and a first P-type control transistor, the pulse amplitude modulation circuit comprising a P-type driving transistor and a second P-type control transistor, and the operation method comprising:

in an emission period, turning on the P-type pulse width compensation transistor, so that the first P-type control transistor is turned on to turn on the second P-type control transistor, so as to turn on the P-type driving transistor; and

driving a light-emitting element to emit light through the P-type driving transistor when the P-type driving transistor is turned on.

16. The operation method of claim 15 , wherein the pulse width modulation circuit comprises a first P-type reset transistor, a second P-type reset transistor and a third P-type reset transistor, the pulse amplitude modulation circuit comprises a fourth P-type reset transistor and a P-type switching transistor, and the operation method further comprising:

in a reset period, providing a light-emitting signal having a disabling level for the P-type pulse width compensation transistor, so that the P-type pulse width compensation transistor is turned off;

in the reset period, providing an inverted light-emitting signal having an enabling level for the third and fourth P-type reset transistors, so that the third and fourth P-type reset transistors are turned on; and

in the reset period, providing a control signal having the enabling level for the first and second P-type reset transistors and the P-type switching transistor, so that the first and second P-type reset transistors and the P-type switching transistor are turned on, and the P-type driving transistor is turned off.

17. The operation method of claim 15 , wherein the pulse width modulation circuit comprises a data writing transistor, the pulse amplitude modulation circuit comprises a P-type threshold voltage compensation transistor and a P-type switching transistor, and the operation method further comprising:

in a compensation and data input period, providing a light-emitting signal having a disabling level for the P-type pulse width compensation transistor, so that the P-type pulse width compensation transistor is turned off;

in the compensation and data input period, providing a control signal having an enabling level for the data writing transistor, so that the data writing transistor is turned on, and the data writing transistor writes a data voltage to a control terminal of the first P-type control transistor; and

in the compensation and data input period, providing the control signal having the enabling level for the P-type switching transistor, so that the P-type switching transistor is turned on, and the P-type threshold voltage compensation transistor discharges a node to a reference voltage plus a threshold voltage of the P-type threshold voltage compensation transistor.

18. The operation method of claim 17 , further comprising:

in the emission period, providing the light-emitting signal having the enabling level for the P-type pulse width compensation transistor, so that the P-type pulse width compensation transistor is turned on; and

in the emission period, when the data voltage is greater than a sawtooth voltage received by the P-type pulse width compensation transistor, turning on the first P-type control transistor to turn on the second P-type control transistor, and providing a driving voltage having the enabling level for the second P-type control transistor, so that the P-type driving transistor is turned on to drive the light-emitting element to emit the light.

19. The operation method of claim 15 , wherein the pulse width modulation circuit comprises a P-type reset transistor electrically connected to the first P-type control transistor, the pulse amplitude modulation circuit comprises a P-type reset transistor electrically connected to the second P-type control transistor, and the operation method further comprising:

in a turn-off period, providing a light-emitting signal having a disabling level for the P-type pulse width compensation transistor, so that the P-type pulse width compensation transistor is turned off; and

in the turn-off period, providing an inverted light-emitting signal having an enabling level for the P-type reset transistor of the pulse width modulation circuit and the P-type reset transistor of the pulse amplitude modulation circuit, so that the P-type reset transistor of the pulse width modulation circuit and the P-type reset transistor of the pulse amplitude modulation circuit are turned on.