Dual-mode column amplifier
Examples include an image sensor comprising a pixel array having at least one column of addressable pixel sensors, and a column amplifier coupled to the at least one column of addressable pixel sensors, the column amplifier comprising a transistor bank including a plurality of transistors, and mode select circuitry coupled to the transistor bank and configured to establish one or more connections among the plurality of transistors to configure the column amplifier to operate in one of a differential mode of operation and a single-ended mode of operation.
1. An image sensor comprising:
a pixel array having at least one column of addressable pixel sensors; and
a column amplifier coupled to the at least one column of addressable pixel sensors, the column amplifier comprising a transistor bank including a plurality of transistors, and mode select circuitry coupled to the transistor bank and configured to establish one or more connections among the plurality of transistors to configure the column amplifier to operate in one of a differential mode of operation and a single-ended mode of operation;
wherein the mode select circuitry comprises a plurality of switches, the plurality of switches including a first subset of switches and a second subset of switches, the second subset of switches being logical complements of the first subset of switches; and
wherein when the first subset of switches are in a closed position and the second subset of switches are in an open position, the column amplifier is configured into the differential mode of operation, and when the first subset of switches are in the open position and the second subset of switches are in the closed position, the column amplifier is configured into the single-ended mode of operation.
2. The image sensor of claim 1 , wherein the plurality of transistors includes at least one pair of transistors, and wherein the mode select circuitry is configured to connect together two transistors forming each pair of transistors of the at least one pair of transistors to configure the column amplifier into the single-ended mode of operation.
3. The image sensor of claim 1 , wherein the plurality of transistors comprises a first transistor, a first chain of transistors coupled between a supply voltage node and the first transistor, and a second chain of transistors coupled between the supply voltage node and the first transistor.
4. The image sensor of claim 3 , wherein, to configure the column amplifier into the single-ended mode of operation, the mode select circuitry is configured to connect together pairs of transistors to form a third chain of transistors coupled between the supply voltage node and a ground node, each pair of transistors including one transistor from the first chain of transistors and a matching transistor from the second chain of transistors.
5. The image sensor of claim 4 , wherein for each pair of transistors, the matching transistor from the second chain of transistors has a same size as the one transistor from the first chain of transistors.
6. The image sensor of claim 1 , wherein the column amplifier is configured to receive an input voltage from the at least one column of addressable pixel sensors and to provide an output voltage based on the input voltage.
7. The image sensor of claim 6 , further comprising:
an analog-to-digital converter (ADC) coupled to the column amplifier and configured to receive and digitize the output voltage to provide a digital signal; and
a processor coupled to the ADC and configured to receive and process the digital signal.
8. The image sensor of claim 7 , wherein the processor is further configured to provide a control input to the mode select circuitry to control the mode select circuitry to configure the column amplifier between the differential mode of operation and the single-ended mode of operation.
9. A column amplifier circuit comprising:
a first transistor coupled between a voltage supply terminal and a first node, the first transistor having a first control terminal coupled to a first input terminal;
a second transistor coupled between an output terminal and the first node, the second transistor having a second control terminal coupled to a second input terminal;
a third transistor coupled between the voltage supply terminal and the first transistor, the third transistor having a third control terminal;
a fourth transistor coupled between the output terminal and the second transistor, the fourth transistor having a fourth control terminal coupled to the third control terminal of the third transistor;
a fifth transistor coupled between the first node and a ground terminal, the fifth transistor having a fifth control terminal; and
switching circuitry including
a first switch that selectively couples the first input terminal to the second input terminal,
a second switch that selectively couples together a second node positioned between the first and third transistors and a third node positioned between the second transistor and the fourth transistor,
a third switch that selectively couples the third transistor to the output terminal,
a fourth switch that selectively couples the first node to the ground terminal, and
a first switching device that selectively couples the fifth control terminal of the fifth transistor between a first bias voltage terminal and the ground terminal.
10. The column amplifier circuit of claim 9 , wherein the first switching device includes a pair of fifth switches that are logical complements of one another.
11. The column amplifier circuit of claim 10 , further comprising:
a sixth transistor coupled between the third transistor and the voltage supply terminal, the sixth transistor having a sixth control terminal; and
a seventh transistor coupled between the output terminal and the voltage supply terminal, the seventh transistor having a seventh control terminal coupled to the sixth control terminal of the sixth transistor.
12. The column amplifier circuit of claim 11 , further comprising:
an eighth transistor coupled between the sixth transistor and the voltage supply terminal, the eighth transistor having an eighth control terminal; and
a ninth transistor coupled between the seventh transistor and the voltage supply terminal, the ninth transistor having a ninth control terminal coupled to the eighth control terminal of the eighth transistor.
13. The column amplifier circuit of claim 12 , wherein the switching circuitry further comprises:
a second switching device that selectively couples the eight and ninth control terminals of the eighth and ninth transistors, respectively, to one of a fourth node and a second bias voltage terminal, the fourth node being positioned between the third and sixth transistors; and
a sixth switch that selectively couples a fifth node to a sixth node, the fifth node being positioned between the sixth and eighth transistors and the sixth node being positioned between the seventh and ninth transistors.
14. The column amplifier circuit of claim 13 , wherein the second switching device includes a pair of seventh switches that are logical complements of one another.
15. The column amplifier of claim 13 , wherein the first, second, third, fourth, and sixth switches are configured to be actuated as a group between an open position and a closed position such that when the first switch is in the open position, the second, third, fourth and sixth switches are in the open position, and when the first switch is in the closed position, the second, third, fourth and sixth switches are in the closed position.
16. The column amplifier circuit of claim 15 , wherein the first switching device is configured to couple the fifth control terminal of the fifth transistor to the ground terminal when the first switch is in the closed position and to couple the fifth control terminal of the fifth transistor to the first bias voltage terminal when the first switch is in the open position; and
wherein the second switching device is configured to couple the eighth and ninth control terminals of the eighth and ninth transistors, respectively, to the fourth node when the first switch is in the open position, and to couple the eighth and ninth control terminals of the eighth and ninth transistors, respectively, to the second bias voltage terminal when the first switch is in the closed position.
17. The column amplifier circuit of claim 16 , wherein the third and fourth control terminals of the third and fourth transistors, respectively, are coupled to a third bias voltage terminal; and
wherein sixth and seventh control terminals of the sixth and seventh transistors, respectively, are coupled to a fourth bias voltage terminal.
18. A column amplifier circuit comprising:
a first transistor having a first control terminal switchably coupled to one of a first bias voltage terminal and a ground terminal;
a first transistor chain coupled between a voltage supply terminal and a first node, the first transistor chain including a second transistor coupled to first node, and a plurality of first chain transistors coupled between the second transistor and the voltage supply terminal, wherein the second transistor has a has a second control terminal coupled to a first input terminal;
a first switch configured to selectively couple the first node to the ground terminal; and
a second transistor chain coupled between the voltage supply terminal and the first node, the second transistor chain including a third transistor coupled between the first node and an output terminal, and a plurality of second chain transistors coupled between the third transistor and the voltage supply terminal,
wherein the third transistor has a third control terminal coupled to a second input terminal that is switchably coupled to the first input terminal,
wherein each first chain transistor of the plurality of first chain transistors has a control terminal connected to a control terminal of a respective second chain transistor of the plurality of second chain transistors, and
wherein the plurality of first chain transistors and the plurality of second chain transistors are switchably coupled together in pairs.