IP Library Granted Patent US 11,750,802
Granted Patent B2
US 11,750,802 · App. 18/073,136 · Granted Sep 5, 2023

Method and device for processing video signal by using inter prediction

Inventors: Seethal Paluri (Seoul, KR); Seunghwan Kim (Seoul, KR)
Assignee: LG ELECTRONICS INC.
H04N19/105H04N19/503H04N19/70
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Quick Facts
Patent No.
US 11,750,802
App. No.
18/073,136
Granted
Sep 5, 2023
Kind
B2
Abstract

Embodiments of the disclosure provide methods and devices for decoding video signals using inter prediction. According to an embodiment of the disclosure, a method for processing a video signal comprises constructing a reference picture list of a current picture in the video signal and performing a prediction for a current picture by using the reference picture list, wherein constructing the reference picture list comprising, if a first entry of the reference picture list corresponds to a short-term reference picture (STRP), obtaining a picture order count (POC) difference between a picture related to the first entry and another picture, and if a second entry of the reference picture list corresponds to a long-term reference picture (LTRP), obtaining a POC modulo value of a picture related to the second entry. A reference picture list for identifying a picture may be generated in a simplified and effective manner. Thus, the compression performance may be increased, and the computation time may be decreased.

Claims (53)

1. An apparatus for decoding a video signal, comprising:

a memory configured to store the video signal; and

a processor coupled with the memory,

wherein the processor is configured to:

obtain a number of entries included in a reference picture list of a current picture;

mark each of entries of the reference picture list as a short-term reference picture (STRP) or a long-term reference picture (LTRP) by the number of entries; and

derive prediction samples for the current picture based on the reference picture list,

wherein the number of entries has a maximum value as a maximum required size of a decoded picture buffer plus 14.

2. The apparatus of claim 1 , wherein for marking each of entries, the processor is further configured to:

obtain a picture order count (POC) difference between a reference picture related to an entry marked as the STRP and another picture in the reference picture list; and

obtain a POC modulo value of a picture related to an entry marked as the LTRP.

3. The apparatus of claim 2 , wherein the POC difference is an absolute value of a POC of the another picture minus a POC of the reference picture related to the entry marked as the STRP.

4. The apparatus of claim 3 , wherein for marking each of entries, the processor is further configured to:

obtain a flag indicating a sign of the POC difference based on that the absolute value is greater than 0.

5. The apparatus of claim 2 , wherein the another picture is the current picture based on that the entry marked as the STRP is a first STRP entry in the marking of each of entries of the reference picture, or the another picture is a previous STRP in the reference picture list based on that the entry marked as the STRP is not the first STRP in the marking of each of entries of the reference picture.

6. The apparatus of claim 1 , wherein for marking each of entries, the processor is configured to:

obtain a number of STRP entries and LTRP entries; and

perform a STRP marking by the number of STRP entries, and perform a LTRP marking by the number of LTRP entries.

7. The apparatus of claim 1 , wherein for marking each of entries, the processor is configured to:

obtain a flag including information about whether an entry of the reference picture list corresponds to an STRP entry or an LTRP entry; and

determine whether the entry of the reference picture list corresponds to the STRP entry or the LTRP entry based on the flag.

8. An apparatus of encoding a video signal, comprising:

a memory configured to store the video signal; and

a processor coupled with the memory,

wherein the processor is configured to:

construct a reference picture list of a current picture; and

generate code information for constructing the reference picture list,

wherein the code information comprises a number of entries of the reference picture list, and

wherein the number of entries has a maximum value as a maximum required size of a decoded picture buffer plus 14.

9. The apparatus of claim 8 , wherein the code information further comprises:

a picture order count (POC) difference between a reference picture related to an entry marked as a short-term reference picture (STRP) and another picture in the reference picture list; and

a POC modulo of a picture related to an entry marked as a long-term reference picture (LTRP) in the reference picture list.

10. The apparatus of claim 9 , wherein the POC difference is an absolute value of a POC of the another picture minus a POC of the reference picture related to the entry marked as the STRP.

11. The apparatus of claim 10 , wherein the code information further comprises a flag indicating a sign of the POC difference for an entry of which the absolute value of the POC difference is greater than 0.

12. The apparatus of claim 9 , wherein the another picture is the current picture based on that the entry marked as the STRP is a first STRP entry in the code information, or the another picture is a previous STRP in the reference picture list based on that the entry marked as the STRP is not the first STRP in the code information.

13. The apparatus of claim 8 , wherein the code information further comprises a flag including information about whether an entry of the reference picture list corresponds to an STRP entry or an LTRP entry.

14. The apparatus of claim 8 , wherein the processor is further configured to:

load the code information in a sequence parameter set (SPS), picture parameter set (PPS), or slice header in a bitstream related to the video signal.

15. An apparatus of transmitting data for an image, comprising:

at least one processor configured to obtain a bitstream for the image; and

a transmitter configured to transmit the data comprising the bitstream,

wherein the at least one processor is configured to:

construct a reference picture list of a current picture; and

generate code information for constructing the reference picture list,

wherein the code information comprises a number of entries of the reference picture list, and

wherein the number of entries has a maximum value as a maximum required size of a decoded picture buffer plus 14.

16. The apparatus of claim 15 , wherein the code information further comprises:

a picture order count (POC) difference between a reference picture related to an entry marked as a short-term reference picture (STRP) and another picture in the reference picture list; and

a POC modulo of a picture related to an entry marked as a long-term reference picture (LTRP) in the reference picture list.

17. The apparatus of claim 16 , wherein the POC difference is an absolute value of a POC of the another picture minus a POC of the reference picture related to the entry marked as the STRP.

18. The apparatus of claim 17 , wherein the code information further comprises a flag indicating a sign of the POC difference for an entry of which the absolute value of the POC difference is greater than 0.

19. The apparatus of claim 16 , wherein the another picture is the current picture based on that the entry marked as the STRP is a first STRP entry in the marking of each of entries of the reference picture, or the another picture is a previous STRP in the reference picture list based on that the entry marked as the STRP is not the first STRP in the marking of each of entries of the reference picture.

20. The apparatus of claim 15 , wherein the code information further comprises a flag including information about whether an entry of the reference picture list corresponds to an STRP entry or an LTRP entry.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: LG ELECTRONICS INC.
To: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
Reel/Frame 066384/0462 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2022
From: PALURI, SEETHAL; KIM, SEUNGHWAN
To: LG ELECTRONICS INC.
Reel/Frame 061944/0665 →
Continuity (5)
Continuation 17306212 · May 3, 2021
Continuation 16942040 · Jul 29, 2020
Continuation PCTKR2020000032 · Jan 2, 2020
Provisional Application 62787384 · Jan 2, 2019
Related Publication 20230118101A1 · Apr 20, 2023