Semiconductor device with secure access key and associated methods and systems
View Patent ↗Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.
1. A semiconductor device, comprising:
a nonvolatile memory configured to store an access key; and
peripheral circuitry coupled to the nonvolatile memory and configured to:
receive a signal from a host device;
retrieve the access key from the nonvolatile memory in response to receiving the signal; and
transmit the access key to the host device using one or more pins designated for otherwise receiving inputs only.
2. The semiconductor device of claim 1 , wherein the peripheral circuitry is configured to activate design-for-test (DFT) functions of the semiconductor device in response to receiving one or more commands including the access key from the host device.
3. The semiconductor device of claim 2 , wherein the DFT functions includes at least one of:
a command directed to the semiconductor device that is otherwise hidden from the host device;
access to a register of the semiconductor device that is otherwise inaccessible by the host device;
a test mode operation of the semiconductor device that is otherwise unavailable to the host device; or
access to the nonvolatile memory that is otherwise inaccessible by the host device.
4. The semiconductor device of claim 2 , wherein one or more circuits of the semiconductor device configured to perform the DFT functions are coupled to a common internal potential of the semiconductor device.
5. The semiconductor device of claim 1 , wherein the signal corresponds to a predetermined sequence of two or more commands directed to the semiconductor device.
6. The semiconductor device of claim 1 , wherein the signal corresponds to a predetermined combination of two or more voltage levels as a function of time.
7. The semiconductor device of claim 1 , wherein at least one of the one or more pins for transmitting the access key corresponds to an address pin of the semiconductor device.
8. The semiconductor device of claim 1 , wherein the nonvolatile memory includes at least one of fuses, conductive layers of the semiconductor device, not-AND (NAND) flash memory cells, phase change memory (PCM) cells, or magnetic memory cells.
9. A method, comprising:
receiving, at a semiconductor device, a signal from a host device;
retrieving an access key from a nonvolatile memory of the semiconductor device in response to receiving the signal; and
transmitting the access key to the host device using one or more pins designated for otherwise receiving inputs only.
10. The method of claim 9 , further comprising:
activating design-for-test (DFT) functions of the semiconductor device in response to receiving one or more commands including the access key from the host device.
11. The method of claim 10 , wherein activating the DFT functions includes at least one of:
enabling a command directed to the semiconductor device that is otherwise hidden from the host device;
accessing a register of the semiconductor device that is otherwise inaccessible by the host device;
performing a test mode operation of the semiconductor device that is otherwise unavailable to the host device; or
accessing the nonvolatile memory that is otherwise inaccessible by the host device.
12. The method of claim 10 , wherein activating the DFT functions corresponds to activating a common internal potential of the semiconductor device, the common internal potential being coupled to one or more circuits of the semiconductor device configured to perform the DFT functions.
13. The method of claim 9 , wherein the signal corresponds to a predetermined sequence of two or more commands directed to the semiconductor device.
14. The method of claim 9 , wherein the signal corresponds to a predetermined combination of two or more voltage levels as a function of time.
15. The method of claim 9 , wherein at least one of the one or more pins for transmitting the access key corresponds to an address pin of the semiconductor device.
16. A system, comprising:
a host device configured to:
transmit a signal to a semiconductor device; and
receive an access key from the semiconductor device in response to transmitting the signal, wherein:
the semiconductor device is configured to:
receive the signal from the host device;
retrieve the access key from a nonvolatile memory of the semiconductor device in response to receiving the signal; and
transmit the access key to the host device using one or more pins designated for otherwise receiving inputs only.
17. The system of claim 16 , wherein the host device is configured to generate one or more commands directed to the semiconductor device in response to receiving the access key, the one or more commands including the access key, and wherein the semiconductor device is configured to activate design-for-test (DFT) functions of the semiconductor device in response to receiving the one or more commands from the host device.
18. The system of claim 16 , wherein the signal corresponds to a predetermined sequence of two or more commands directed to the semiconductor device.
19. The system of claim 16 , wherein the signal corresponds to a predetermined combination of two or more voltage levels as a function of time.
20. The system of claim 16 , wherein at least one of the one or more pins for transmitting the access key corresponds to an address pin of the semiconductor device.