VIA FORMED USING A PARTIAL PLUG THAT EXTENDS INTO A SUBSTRATE
A method is described including creating a partial through substrate via (TSV) plug in a front side of a wafer, the partial TSV plug having a front side and a back side, the back side of the partial TSV extending through the front side of the substrate. A cavity is etched in a back side of the wafer that exposes the back side of the partial TSV plug. An insulator is applied to the etched back side of the wafer. A back side of the partial TSV plug is exposed by removing one or more of a portion of the insulator and a liner. A conductive material is deposited to connect the exposed, back side of the partial TSV plug to a surface on the back side of the wafer.
1 . A method comprising:
creating a partial through substrate via (TSV) plug in a front side of a wafer having a first and a second layer, the partial TSV plug having a front side and a back side, the back side of the partial TSV extending through a front side of the second layer;
etching a cavity in a back side of the wafer that exposes the back side of the partial TSV plug;
applying an insulator to the etched back side of the wafer;
exposing the back side of the partial TSV plug by removing one or more of a portion of the insulator and a liner; and
depositing a conductive material to connect the exposed, back side of the partial TSV plug to a surface on the back side of the wafer.
2 . The method of claim 1 , further comprising attaching adding a protective insulation layer to the conductive material, the protective insulation layer having a connection region formed therein.
3 . The method of claim 2 , further comprising attaching a conductive connection to the connection region.
4 . The method of claim 3 , wherein the conductive connection is selected from the group consisting of an aluminum pad, a Ni—Au pad, a solder ball, a copper pillar, and any other interconnection technique.
5 . The method of claim 1 , wherein the partial TSV plug has a vertical dimension and a horizontal dimension, and wherein a ratio between the vertical dimension and the horizontal dimension is in a range between 1:4 and 7:1.
6 . The method of claim 1 , wherein creating the partial TSV plug in the front side of the wafer further comprises, applying a plasma to the back side of the substrate to create a void.
7 . The method of claim 6 , further comprising lining or filling the void with a second conductive material.
8 . The method of claim 7 , wherein the second conductive material is selected from the group consisting of Copper, Aluminum, Tungsten, a solder, Tin/Silver, alloys thereof, a conductive ceramic, a conductive polymer, and combinations thereof.
9 . The method of claim 1 , wherein the partial TSV plug extends into one or more of an insulating layer, a routing layer, and an SOI layer.
10 . The method of claim 1 , wherein the back side of the partial TSV plug extends through the front side of the substrate and partially into a bulk of the substrate.
11 . The method of claim 1 , wherein lining the etched back side of the substrate with the insulator further comprises applying the insulator wherein a thickness at a back side of the substrate where the insulator is applied is greater than the thickness of the insulator at the etched portion of the substrate.
12 . The method of claim 11 , wherein the thickness at a back side of the substrate where the insulator is applied is greater than the thickness of the insulator at the etched portion of the substrate and the exposed back side portion of the partial TSV plug.
13 . The method of claim 11 , wherein lining the etched back side of the substrate with the insulator further includes lining a portion of the layer but not the partial TSV plug.
14 . The method of claim 1 , wherein exposing the back side of the partial TSV plug by removing the portion of the insulator further comprises applying a directional etch to the etched back side of the substrate with the insulator.
15 . The method of claim 1 , wherein the partial TSV plug has a vertical dimension and a horizontal dimension, and wherein a ratio between the vertical dimension and the horizontal dimension is equal.
16 . The method of claim 1 , wherein etching the cavity in the back side of the substrate exposes the back side of the partial TSV plug.
17 . A wafer comprising:
an insulating layer;
a substrate below the insulating layer;
a partial TSV plug extending from a front side of the wafer and extending past a back side of the insulating layer into the substrate, the partial TSV plug having a front side and a back side;
an insulator applied to an etched portion of a back side of the substrate and at least a portion of a back side of the partial TSV plug and etched from at least a portion of the back side of the partial TSV plug; and
a conductive layer deposited on the insulator and the etched back side of the partial TSV plug.
18 . The wafer of claim 17 , further comprising a back side insulator below the conductive layer with a connection through to the conductive layer.
19 . The wafer of claim 17 , further comprising one or more routing layers connecting the partial TSV plug to an integrated device or additional stacked circuits connected to the front side of the wafer.
20 . The wafer of claim 17 , wherein the back side of the partial TSV plug extends from the front side of the wafer in or above the insulating layer into a portion of the handle wafer.