Supply current consumption acquisition synchronized with debug data trace

1. A system, comprising:

a microcontroller including a microprocessor;

a debug probe; and

a host configured to, upon startup of the microcontroller, send debug instructions to the debug probe that, when executed by the microcontroller, begin execution of a debug trace within the microcontroller;

wherein the debug probe is configured to send the debug instructions to the microcontroller;

wherein the microcontroller is configured to execute the debug trace according to said debug instructions to generate trace data, the trace data including trace data time stamps;

wherein the debug probe is further configured to: receive a power signal from the host; and sample the power signal and provide the power signal to the microcontroller, with each sampling of the power signal occurring during a different power acquisition cycle;

wherein the host is further configured to periodically send synchronization requests to the debug probe;

wherein the debug probe is further configured to, in response to receipt of each synchronization request: retrieve a current power acquisition cycle number; generate an intermediate synchronization request; and send the intermediate synchronization request to the microcontroller;

wherein the microcontroller is further configured to, in response to receipt of each intermediate synchronization request, send a message to the debug probe, the message including a current execution cycle number of the microprocessor and an associated cycle number time stamp;

wherein the debug probe is further configured to: send the trace data to the host; send the messages to the host; and send the sampled power signal to the host; and

wherein the host is configured to;

determine a trace data time stamp within the trace data where the sampling of the power signal began;

derive a frequency of the microprocessor from the trace data;

determine a ratio between a sampling rate of the power signal and the frequency of the microprocessor; and

align the trace data and the samples of the power signal based upon the ratio and the trace data time stamp within the trace data where the sampling of the power signal began.

2. The system of claim 1 , wherein the debug probe includes a power acquisition circuit that samples the power signal.

3. The system of claim 1 , wherein the debug probe includes a protocol manager that retrieves the current power acquisition cycle number, generates the intermediate synchronization request, sends the intermediate synchronization request to the microcontroller; sends the trace data to the host, sends the messages to the host, and sends the sampled power signal to the host.

4. The system of claim 3 , wherein the protocol manager sends the intermediate synchronization request to the microcontroller via a serial wire debug (SWD) protocol; wherein the microcontroller sends the message to the debug probe via a UART protocol (SWO) and sends the trace data to the debug probe via the SWD protocol.

5. The system of claim 4 , wherein the message is generated within an instrument trace macrocell (ITM) within the microcontroller.

6. The system of claim 3 , wherein the debug probe includes a power acquisition circuit that samples the power signal; wherein the microcontroller is further configured to, upon receipt of each intermediate synchronization request, send a request acknowledgement to the debug probe; wherein the protocol manager is further configured to measure a number of power acquisition cycles between sending of each intermediate synchronization request and receipt of each request acknowledgement, and determine a latency based thereupon; wherein the latency is indicative of accuracy in the alignment between the trace data and the samples of the power signal.

7. A method of aligning trace data and power consumption data in a debugging system, the method comprising:

send debug instructions to a microcontroller within the debugging system, the debug instructions, when executed by the microcontroller, begin execution of a debug trace;

receive a power signal from a host within the debugging system;

sample the power signal and provide the power signal to the microcontroller, with each sampling of the power signal occurring during a different power acquisition cycle;

in response to receipt of each of a number of periodic synchronization requests: retrieve a current power acquisition cycle number; generate an intermediate synchronization request; and send the intermediate synchronization request to the microcontroller;

receive trace data from the microcontroller, the trace data including trace data time stamps;

receive from the microcontroller, in response to the sending of each intermediate synchronization request, a message, the message including a current execution cycle number of a microprocessor within the microcontroller and an associated cycle number time stamp; and

send the trace data to the host, send the messages to the host, and send the sampled power signal to the host so that the host aligns the trace data and the samples of the power signal based upon a trace data time stamp within the trace data where the sampling of the power signal began and a ratio between a sampling rate of the power signal and a frequency of the microprocessor.

8. The method of claim 7 , further comprising deriving the frequency of the microprocessor from the trace data.

9. The method of claim 7 , further comprising;

in response to the sending of each intermediate synchronization request to the microcontroller, receive a request acknowledgement;

measure a number of power acquisition cycles between the sending of each intermediate synchronization request and receipt of each request acknowledgement, and determine a latency based thereupon; and

determine accuracy in the alignment between the trace data and the samples of the power signal from the latency.

10. A method of aligning trace data and power consumption data in a debugging system, the method comprising:

upon startup of a microcontroller within the debugging system, send debug instructions from a host within the debugging system to a debug probe within the debugging system that, when executed by the microcontroller, begin execution of a debug trace;

transmit the debug instructions from the debug probe to the microcontroller;

execute the debug trace at the microcontroller according to said debug instructions to generate trace data, the trace data including trace data time stamps;

receive a power signal, at the debug probe, from the host;

sample the power signal at the debug probe and provide the power signal to the microcontroller, with each sampling of the power signal occurring during a different power acquisition cycle;

periodically send synchronization requests from the host to the debug probe;

in response to receipt of each synchronization request at the debug probe: retrieve a current power acquisition cycle number; generate an intermediate synchronization request; and send the intermediate synchronization request from the debug probe to the microcontroller;

in response to receipt of each intermediate synchronization request at the microcontroller, send a message to the debug probe, the message including a current execution cycle number of a microprocessor within the microcontroller and an associated cycle number time stamp;

send the trace data from the debug probe to the host;

send the messages from the debug probe to the host;

send the sampled power signal from the debug probe to the host;

determine a trace data time stamp within the trace data where the sampling of the power signal began, at the host;

derive a frequency of the microprocessor from the trace data, at the host;

determine a ratio between a sampling rate of the power signal and the frequency of the microprocessor, at the host; and

align the trace data and the samples of the power signal based upon the ratio and the trace data time stamp within the trace data where the sampling of the power signal began, at the host.

11. The method of claim 10 , further comprising:

upon receipt of each intermediate synchronization request at the microcontroller, send a request acknowledgement to the debug probe; and

measure a number of power acquisition cycles between sending of each intermediate synchronization request and receipt of each request acknowledgement at the debug probe, and determine a latency based thereupon;

wherein the latency is indicative of accuracy in the alignment between the trace data and the samples of the power signal.

12. A system, comprising:

a microcontroller including a microprocessor;

a debug probe; and

a host;

wherein the microcontroller is configured to execute a debug trace to generate trace data, the trace data including trace data time stamps;

wherein the debug probe is further configured to: receive a power signal from the host; and sample the power signal and provide the power signal to the microcontroller, with each sampling of the power signal occurring during a different power acquisition cycle;

wherein the host is further configured to periodically send synchronization requests to the debug probe;

wherein the debug probe is further configured to, in response to receipt of each synchronization request: retrieve a current power acquisition cycle number; generate an intermediate synchronization request; and send the intermediate synchronization request to the microcontroller;

wherein the microcontroller is further configured to, in response to receipt of each intermediate synchronization request, send a message to the debug probe, the message including a current execution cycle number of the microprocessor and an associated cycle number time stamp;

wherein the debug probe is further configured to: send the trace data to the host; send the messages to the host; and send the sampled power signal to the host; and

wherein the host is configured to align the trace data and the samples of the power signal based upon a trace data time stamp within the trace data where the sampling of the power signal began, the trace data, and a sampling rate of the power signal.

13. The system of claim 12 , wherein host is configured to align the trace data and the samples of the power signal based upon a ratio between a sampling rate of the power signal and a frequency of the microprocessor and based upon the trace data time stamp within the trace data where the sampling of the power signal began.

14. The system of claim 12 , wherein the debug probe includes a power acquisition circuit that samples the power signal.

15. The system of claim 12 , wherein the debug probe includes a protocol manager that retrieves the current power acquisition cycle number, generates the intermediate synchronization request, sends the intermediate synchronization request to the microcontroller; sends the trace data to the host, sends the messages to the host, and sends the sampled power signal to the host.

16. The system of claim 15 , wherein the protocol manager sends the intermediate synchronization request to the microcontroller via a serial wire debug (SWD) protocol; wherein the microcontroller sends the message to the debug probe via a UART protocol (SWO) and sends the trace data to the debug probe via the SWD protocol.

17. The system of claim 16 , wherein the message is generated within an instrument trace macrocell (ITM) within the microcontroller.

18. The system of claim 15 , wherein the debug probe includes a power acquisition circuit that samples the power signal; wherein the microcontroller is further configured to, upon receipt of each intermediate synchronization request, send a request acknowledgement to the debug probe; wherein the protocol manager is further configured to measure a number of power acquisition cycles between sending of each intermediate synchronization request and receipt of each request acknowledgement, and determine a latency based thereupon; wherein the latency is indicative of accuracy in the alignment between the trace data and the samples of the power signal.