Cryptographic processor for fully homomorphic encryption (FHE) applications

1. A cryptographic processor, comprising:

a first cryptographic processing module to perform a first logic operation, the first cryptographic processing module configured as a Residue Number System (RNS) architecture and including:

first input circuitry to receive ciphertext input symbols;

a first pipeline stage to perform a first operation on the ciphertext input symbols and to generate a first stage output;

storage circuitry to store constants for use by the first pipeline stage, the storage circuitry to temporarily store the first stage output and to feed a second pipeline stage in a pipelined manner;

at least one Chinese Remainder Theorem (CRT) processing stage;

wherein the second pipeline stage is configured to perform a second operation on the first stage output in a pipelined manner with respect to the first pipeline stage; and

wherein the first cryptographic processing module includes multiple processing slices defining multiple processing channels, each channel to perform operations on signals 64-bits wide or less concurrently with the other processing channels.

2. The cryptographic processor of claim 1 , wherein:

the first input circuitry receives the ciphertext input symbols synchronous with an instruction clock signal; and

wherein a new set of input ciphertext symbols are presented to the first input circuitry each cycle of the instruction clock signal.

3. The cryptographic processor of claim 1 , wherein:

the first cryptographic processing module is configured to perform ciphertext multiplication operations, ciphertext rotation operations, or ciphertext addition operations.

4. The cryptographic processor of claim 1 , wherein:

the storage circuitry includes an input interface that is configured with a bit-width to receive at least one entire ciphertext or key coefficient per cycle of a system clock.

5. The cryptographic processor of claim 1 , wherein:

the first cryptographic processing module is configured as a Large Arithmetic Word Size (LAWS) architecture.

6. The cryptographic processor of claim 5 , wherein:

the first cryptographic processing module includes a single processing slice defining a single processing channel to perform operations on signals that are more than 64-bits wide.

7. The cryptographic processor of claim 1 , further comprising:

a second processing module to perform a second logic operation different than the first logic operation.

8. The cryptographic processor of claim 1 , wherein the storage circuitry includes:

on-chip register circuitry configured to temporarily store the input of each stage.

9. The cryptographic processor of claim 1 , wherein:

the first cryptographic processing module produces outputs with a pre-determined latency of execution cycles and constant throughput.

10. The cryptographic processor of claim 1 , wherein:

the first pipeline stage comprises a stage of number theoretic transform (NTT) circuits to perform an NTT operation as the first operation, the stage of NTT circuits configured to exhibit a predetermined parallelism; and

wherein the second pipeline stage is configured to employ a number of inputs and outputs that match the predetermined parallelism of the stage of NTT circuits.

11. A cryptographic processor, comprising:

a first cryptographic processing module including:

first input circuitry to receive ciphertext input symbols;

a number theoretic transform (NTT) stage to perform an NTT operation on received ciphertext input symbols and to generate an NTT stage output, the NTT stage configured to exhibit a predetermined parallelism;

a second circuit stage that receives the NTT stage output in a pipelined manner;

wherein the second circuit stage is configured to employ a number of inputs and outputs that matches the predetermined parallelism of the NTT circuit, and

wherein the first cryptographic processing module is configured as a Residue Number System (RNS) architecture and includes multiple processing slices defining multiple processing channels, each channel to perform operations on signals 64-bits wide or less concurrently with the other processing channels.

12. The cryptographic processor of claim 11 , wherein:

the first input circuitry receives the ciphertext input symbols synchronous with an instruction clock signal; and

wherein a new set of input ciphertext symbols are presented to the first input circuitry each cycle of the instruction clock signal.

13. The cryptographic processor of claim 11 , wherein:

the first cryptographic processing module is configured to perform ciphertext addition operations or ciphertext multiplication operations or ciphertext rotation operations.

14. The cryptographic processor of claim 11 , wherein:

the first cryptographic processing module produces outputs with a pre-determined latency of execution cycles and constant throughput.

15. A cryptographic processor, comprising:

a first cryptographic processing module including:

first input circuitry to receive ciphertext input symbols;

a number theoretic transform (NTT) stage to perform an NTT operation on received ciphertext input symbols and to generate an NTT stage output, the NTT stage configured to exhibit a predetermined parallelism;

a second circuit stage that receives the NTT stage output in a pipelined manner;

wherein the second circuit stage is configured to employ a number of inputs and outputs that matches the predetermined parallelism of the NTT circuit; and

wherein the first cryptographic processing module is configured as a Large Arithmetic Word Size (LAWS) architecture and includes a single processing slice defining a single processing channel to perform operations on signals that are more than 64-bits wide.

16. A method of operation in a cryptographic processor, the method comprising:

receiving ciphertext input symbols with first input circuitry;

performing a number theoretic transform (NTT) operation on the received ciphertext input symbols with an NTT stage and generating an NTT stage output, the NTT stage configured to exhibit a predetermined parallelism;

receiving the NTT stage output in a pipelined manner with a second pipeline stage;

configuring the second pipeline stage to employ a number of inputs and outputs that matches the predetermined parallelism of the NTT circuit; and

configuring the cryptographic processor as a Residue Number System (RNS) architecture and including multiple processing slices defining multiple processing channels, each channel to perform operations on signal 64-bits wide or less concurrently with the other processing channels.

17. A method of operation in a cryptographic processor, the method comprising:

receiving ciphertext input symbols with first input circuitry;

performing a number theoretic transform (NTT) operation on the received ciphertext input symbols with an NTT stage and generating an NTT stage output, the NTT stage configured to exhibit a predetermined parallelism;

receiving the NTT stage output in a pipelined manner with a second pipeline stage;

configuring the second pipeline stage to employ a number of inputs and outputs that matches the predetermined parallelism of the NTT circuit; and

configuring the cryptographic processor as a Large Arithmetic Word Size (LAWS) architecture and including a single processing slice defining a single processing channel to perform operations on signals that are more than 64-bits wide.