Data transfer in port switch memory

1. An apparatus, comprising:

a first number of memory devices coupled to a host via a first number of ports; and

a second number of memory devices coupled to the first number of memory devices via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices via the second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host during a same clock cycle that the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices.

2. The apparatus of claim 1 , wherein the first number of memory devices are configured to receive a first number of commands from the host that include addresses to the first number of memory devices to transfer data between the first number of memory devices and the host.

3. The apparatus of claim 1 , wherein the first number of memory devices are configured to execute a first number of commands by sending a status signal from a controller coupled to the first and second number of memory devices to the host.

4. The apparatus of claim 1 , wherein the first number of memory devices are configured to receive a first number of commands from the host in response to a change in a ready/wait signal sent from a controller coupled to the first and second number of memory devices to the host.

5. The apparatus of claim 1 , wherein the apparatus is a non-volatile dual in-line memory module (NVDIMM), the first number of memory devices are volatile memory devices, and the second number of memory devices are non-volatile memory devices.

6. An apparatus, comprising:

memory module, wherein the memory module includes a first number of memory devices and a second number of memory devices coupled to a controller, wherein the memory module is coupled to a host, and wherein the memory module is configured to:

receive a first number of commands for execution on a first portion of the first number of memory devices via a first number of ports; and

receive a second number of commands for execution on a second portion of the first number of memory devices on the memory module via the first number of ports wherein a multiplexor is configured to isolate the second portion of the first number of memory devices from the host in response to memory module receiving the second number of commands.

7. The apparatus of claim 6 , wherein the memory module is configured to receive a third number of commands for execution on a first portion of the second number of memory devices via a second number of ports.

8. The apparatus of claim 7 , wherein the first number of commands and the third number of commands are executed during a same clock cycle.

9. The apparatus of claim 6 , wherein the second portion of the first number of memory devices is configured as cache for a second portion of the second number of memory devices.

10. The apparatus of claim 6 , wherein the second number of commands include addresses to a second portion of the second number of memory devices.

11. The apparatus of claim 6 , wherein the second portion of the first number of memory devices is configured as cache for another memory module coupled to the host.

12. A method, comprising:

receiving, from a host device, a first command via a first port of a first memory die of a memory device on a memory module, wherein the memory device comprises a first bus coupled between the first port and the host device and a second bus coupled between a second port of the first memory die and a controller of the memory module;

receiving, from the controller of the memory module, a second command via a second port of a second memory die of the memory device, wherein a first port of the second memory die is coupled to the first bus of the memory device and the second port of the second memory die is coupled to the second bus of the memory device; and

executing the first command at the first memory die of the first device and the second command at the second memory die of the first device, wherein first memory die and the second memory die are paired together via the first port and second port and wherein the second memory die is isolated from the host device by a multiplexor and the first port.

13. The method of claim 12 , further comprising isolating the first memory die from the controller via the multiplexor and the second port.

14. The method of claim 12 , wherein the first command and the second command are executed during a same clock cycle.

15. The method of claim 12 , wherein executing the second command comprises transferring data from the second memory die to another device of the memory module via the controller of the memory module.

16. The method of claim 12 , further comprising executing a third command to transfer data between the first memory die and the second memory die via the controller of the memory module to reconcile data in the first memory die and second memory die after executing the first command and the second command.

17. The method of claim 12 , further comprising executing the first command at the first memory die of the first device while executing the second command at the second memory die of the first device.