Advanced computational pixel imagers with multiple in-pixel counters
A computational pixel imaging device can include multiple digitizing counters per pixel that can be used to execute simultaneous signal-processing threads on acquired image data. The imaging device can also include infinite dynamic range sensing and perform signal down-sampling.
1. A computational pixel imaging system comprising a computational pixel imager having a plurality of pixels, each pixel including:
a detector;
a detector biasing line arranged to apply a bias or supply voltage modulated at a first frequency to the detector;
one or more counters arranged to digitize a signal output from the detector; and
a mixer, wherein an output from the mixer is used to determine a periodicity of count-up and count-down cycles for one or more of the counters.
2. The computational pixel imaging system of claim 1 , further comprising:
a light source arranged to illuminate an object; and
a modulation source configured to modulate the intensity of light from the light source at a second frequency.
3. The computational pixel imaging system of claim 2 , wherein a difference between the first frequency and the second frequency is between 10 kilohertz and 500 kilohertz.
4. The computational pixel imaging system of claim 1 , wherein the output from the mixer is used to determine the periodicity for two counters that count up and count down cyclically but are shifted in phase with respect to each other by 90 degrees.
5. The computational pixel imaging system of claim 1 , wherein the detector is a phototransistor.
6. The computational pixel imaging system of claim 1 , wherein at least one of the counters is configured for infinite dynamic range counting.
7. A computational pixel imaging system comprising a computational pixel imager having a plurality of pixels, each pixel including:
a detector;
a detector biasing line arranged to apply a bias or supply voltage modulated at a first frequency to the detector;
one or more counters arranged to digitize a signal output from the detector; and
a current-to-frequency converter arranged to receive a signal from the detector, wherein an output from the current-to-frequency converter is provided to one or more of the counters.
8. A method of down-sampling with a pixel integrated circuit, the method comprising:
illuminating an object with light modulated at a first frequency;
receiving, at a detector of a pixel integrated circuit, the modulated light returned from the object; and
modulating a bias or supply applied to the detector with a second frequency that differs from the first frequency, wherein the first frequency differs from the second frequency by an amount between 10 kilohertz and 500 kilohertz.
9. The method of claim 8 , further comprising providing an output from the detector for digitization by one or more counters.
10. The method of claim 9 , further comprising controlling a periodicity of a count-up and count-down cycle for at least one of the counters to be at a third frequency that is the difference between the first frequency and the second frequency.
11. The method of claim 9 , wherein illuminating the object further includes projecting a pattern of the light onto the object.
12. The method of claim 11 , further comprising:
receiving with an array of the pixel integrated circuits, and image of the object and pattern;
analyzing the pattern; and
determining three-dimensional geometry of the object.
13. A method of multi-thread processing in a pixel of an array of pixels, the method comprising:
receiving photons at a detector in a first pixel in the array;
controlling a first counter connected to the detector and located in the first pixel to create a first digital signal for first image data in response to the received photons;
controlling a second counter connected to the detector and located in the first pixel to create a second digital signal for second image data in response to the received photons;
performing a first computational algorithm with a first value from the first counter to compute the first image data; and
while performing the first computational algorithm, performing a second computational algorithm different from the first computational algorithm with a second value from the second counter to compute the second image data.
14. The method of claim 13 , wherein one or both of the first computational algorithm and second computational algorithm is a spatial or temporal filtering function performed on an image acquired by the array of pixels.
15. The method of claim 13 , wherein one or both of the first computational algorithm and second computational algorithm is a convolution or correlation function performed on an image acquired by the array of pixels.
16. The method of claim 13 , wherein one or both of the first computational algorithm and second computational algorithm is an image shift operation performed on an image acquired by the array of pixels.
17. The method of claim 13 , wherein one or both of the first computational algorithm and second computational algorithm is a background subtraction function performed on an image acquired by the array of pixels.
18. The method of claim 13 , further comprising:
illuminating an object with light modulated at a first frequency;
receiving, at the detector, the modulated light returned from the object; and
modulating a bias or supply applied to the detector with a second frequency that differs from the first frequency.
19. The method of claim 18 , further comprising controlling a periodicity of a count-up and count-down cycle for at least one of the first counter and second counter to be at a third frequency that is the difference between the first frequency and the second frequency.
20. The method of claim 13 , wherein one or both of the first and second counters is or are arranged for infinite dynamic range counting.
21. A computational pixel imager having an array of pixels, at least one pixel in the array comprising:
a detector;
a first transistor connected to the detector; and
two or more second transistors connected in parallel between the first transistor and two or more signal converters.
22. The computational pixel imager of claim 21 , wherein the two or more signal converters are current-to-frequency converters.
23. The computational pixel imager of claim 21 , further comprising one or more counters connected to at least one of the two or more signal converters.
24. The computational pixel imager of claim 23 , further comprising:
a multiplexer connected to two or more outputs of the two or more signal converters; and
one or more counters arranged to receive an output from the multiplexer.
25. The computational pixel imager of claim 23 , further comprising:
a b-bit counter connected to an output of a signal converter of the two or more signal converters;
a data line arranged to transmit a value of a most significant bit of the b-bit counter; and
read-out circuitry configured to read the most significant bit at a higher read-out rate than a read-out rate for other bits of the b-bit counter.
26. The computational pixel imager of claim 23 , further comprising:
a detector biasing line arranged to apply a bias or supply voltage modulated at a first frequency to the detector; and
one or more counters arranged to digitize a signal output from at least one of the two or more signal converters.