Partitioning responsive to processors having a disparate number of memory modules

1. A computer program product comprising a non-volatile computer readable medium and non-transitory program instructions embodied therein, the program instructions being configured to be executable by a processor of a baseboard management controller in a multi-processor system to cause the processor to perform operations comprising:

detecting a number of memory modules connected to each of a plurality of central processing units in the multi-processor system during boot;

initiating operation of the multi-processor system as a single unified node in response to each of the plurality of central processing units being connected to an equal number of memory modules; and

initiating partitioning of the multi-processor system into a first partitioned node and a second partitioned node in response to a first set of one or more of the central processing units each being connected to a first number of memory modules and a second set of one or more of the central processing units each being connected to a second number of memory modules that is different than the first number of memory modules.

2. The computer program product of claim 1 , wherein the first partitioned node includes the one or more central processing units that are connected to the first number of memory modules, and wherein the second partitioned node includes the one or more central processing units that are connected to the second number of memory modules.

3. The computer program product of claim 2 , the operations further comprising:

determining that the first number of memory modules in the first partitioned node is greater than the second number of memory modules in the second partitioned node; and

initiating configuration of one or more of the memory modules in the first partitioned node that are connected through a Compute Express Link device to be shared by the one or more central processing units of the first partitioned node and the one or more central processing units of the second partitioned node.

4. The computer program product of claim 1 , wherein initiating partitioning of the multi-processor system into the first partitioned node and the second partitioned node includes sending an instruction to disable one or more processor interconnects between the first set of central processing units and the second set of central processing units, and wherein the first set of central processing units is operable as a first independent node and the second set of central processing units is operable as a second independent node.

5. The computer program product of claim 4 , wherein the instruction is sent to a firmware interface.

6. The computer program product of claim 5 , wherein the firmware interface is a unified extensible firmware interface.

7. The computer program product of claim 5 , wherein the number of memory modules connected to each of the plurality of central processing units is identified before booting the firmware interface.

8. The computer program product of claim 7 , wherein the instruction to disable one or more processor interconnects between the first set of central processing units and the second set of central processing units is an instruction to prevent initialization of the one or more processor interconnects between the first set of central processing units and the second set of central processing units during boot.

9. The computer program product of claim 4 , wherein the multi-processor system is a host processor module, wherein the baseboard management controller is installed on a system management module that is selectively connectable to the host processor module, and wherein the system management module manages operation of the host processor module.

10. The computer program product of claim 9 , wherein the instruction is sent to a field-programmable gate array on the host processor module.

11. The computer program product of claim 10 , wherein the instruction that is sent to the field-programmable gate array on the host processor module instructs the field-programmable gate array to enter a first mode for operating all resources as a single unified node with the one or more processor interconnects enabled or a second mode for operating the system as a partitioned system including the first and second independent nodes with the one or more processor interconnects disabled.

12. The computer program product of claim 1 , the operations further comprising:

obtaining an inventory of one or more resource types in the multi-processor system before the firmware interface boots, wherein the one or more resource types include data storage devices and/or input/output devices; and

initiating partitioning of resources of the one or more resource type between the first and second independent nodes.

13. The computer program product of claim 12 , the operations further comprising:

identifying, for the one or more resource types, an amount of resources within the multi-processor system that are of the same resource type;

determining a ratio of a number of central processing units in the first partitioned node to a number of central processing units in the second partitioned node; and

assigning, for the one or more resource types, the identified amount of the resource between the first partitioned node and the second partitioned node to approximate the ratio.

14. The computer program product of claim 13 , wherein assigning, for the one or more resource types, the identified amount of the resource between the first partitioned node and the second partitioned node to approximate the ratio, includes assigning a first group of resources of the multi-processor system to the first partitioned node and assigning a second group of resources of the multi-processor system to the second partitioned node, wherein the first and second groups include at least one data storage device and at least one input/output device.

15. A method comprising:

detecting a number of memory modules connected to each of a plurality of central processing units in the multi-processor system during a boot process;

initiating operation of the multi-processor system as a single unified node in response to each of the plurality of central processing units being connected to an equal number of memory modules; and

initiating partitioning of the multi-processor system into a first partitioned node and a second partitioned node in response to a first set of one or more of the central processing units each being connected to a first number of memory modules and a second set of one or more of the central processing units each being connected to a second number of memory modules that is different than the first number of memory modules.

16. The method of claim 15 , wherein the first partitioned node includes the one or more central processing units that are connected to the first number of memory modules, and wherein the second partitioned node includes the one or more central processing units that are connected to the second number of memory modules.

17. The method of claim 16 , further comprising:

determining that the first number of memory modules in the first partitioned node is greater than the second number of memory modules in the second partitioned node; and

initiating configuration of one or more of the memory modules in the first partitioned node that are connected through a Compute Express Link device to be shared by the one or more central processing units of the first partitioned node and the one or more central processing units of the second partitioned node.

18. The method of claim 15 , wherein initiating partitioning of the multi-processor system into the first partitioned node and the second partitioned node includes sending an instruction to disable one or more processor interconnects between the first set of central processing units and the second set of central processing units, and wherein the first set of central processing units is operable as a first independent node and the second set of central processing units is operable as a second independent node.

19. The method of claim 18 , wherein the instruction is sent to a firmware interface.

20. The method of claim 19 , wherein the number of memory modules connected to each of the plurality of central processing units is identified before booting the firmware interface.