VARIABLE-LENGTH INSTRUCTION BUFFER MANAGEMENT
A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
1 - 19 . (cancelled)
20 . An apparatus comprising:
memory to include variable-length instructions; and
at least one processor to at least:
access a first variable-length instruction of the variable-length instructions, the first variable-length instruction including an operation to be performed on an altered form of a vector referenced at a first memory location;
generate the altered form of the vector as specified by the first variable-length instruction; and
perform the operation on the altered form of the vector, the vector referenced at the first memory location to remain unaltered after the operation is performed.
21 . The apparatus of claim 20 , wherein the altered form of the vector includes swizzled elements of the vector referenced at the first memory location.
22 . The apparatus of claim 20 , wherein the altered form of the vector includes inverted elements of the vector referenced at the first memory location.
23 . The apparatus of claim 20 , wherein the altered form of the vector includes substituted values for elements of the vector referenced at the first memory location.
24 . The apparatus of claim 20 , wherein the altered form of the vector includes at least one element of the vector referenced at the first memory location that is both swizzled and inverted.
25 . The apparatus of claim 20 , wherein the at least one processor is to generate the altered form of the vector by:
identifying a first element of the vector referenced at the first memory location based on a first field of the first variable-length instruction; and
at least one of changing a position or altering a value of the first element of the vector based on a second field of the first variable-length instruction to generate a target element of the altered form of the vector.
26 . Computer readable memory comprising computer readable instructions that, when executed by at least one processor, cause the at least one processor to at least:
access a variable-length instruction including an operation to be performed on an altered form of a vector referenced at a first memory location;
generate the altered form of the vector as specified by the variable-length instruction; and
perform the operation on the altered form of the vector, the vector referenced at the first memory location to remain unaltered after the operation is performed.
27 . The computer readable memory of claim 26 , wherein the altered form of the vector includes swizzled elements of the vector referenced at the first memory location.
28 . The computer readable memory of claim 26 , wherein the altered form of the vector includes inverted elements of the vector referenced at the first memory location.
29 . The computer readable memory of claim 26 , wherein the altered form of the vector includes substituted values for elements of the vector referenced at the first memory location.
30 . The computer readable memory of claim 26 , wherein the altered form of the vector includes at least one element of the vector referenced at the first memory location that is both swizzled and inverted.
31 . The computer readable memory of claim 26 , wherein the computer readable instructions, when executed, cause the at least one processor to generate the altered form of the vector by:
identifying a first element of the vector referenced at the first memory location based on a first field of the variable-length instruction; and
at least one of changing a position or altering a value of the first element of the vector based on a second field of the variable-length instruction to generate a target element of the altered form of the vector.
32 . A method comprising:
accessing a variable-length instruction including an operation to be performed on an altered form of a vector referenced at a first memory location;
generating the altered form of the vector as specified by the variable-length instruction; and
performing, by executing an instruction with at least one processor, the operation on the altered form of the vector, the vector referenced at the first memory location to remain unaltered after the operation is performed.
33 . The method of claim 32 , wherein the altered form of the vector includes swizzled elements of the vector referenced at the first memory location.
34 . The method of claim 32 , wherein the altered form of the vector includes inverted elements of the vector referenced at the first memory location.
35 . The method of claim 32 , wherein the altered form of the vector includes substituted values for elements of the vector referenced at the first memory location.
36 . The method of claim 32 , wherein the altered form of the vector includes at least one element of the vector referenced at the first memory location that is both swizzled and inverted.
37 . The method of claim 32 , wherein the generating of the altered form of the vector includes:
identifying a first element of the vector referenced at the first memory location based on a first field of the variable-length instruction; and
at least one of changing a position or altering a value of the first element of the vector based on a second field of the variable-length instruction to generate a target element of the altered form of the vector.