Method and system for reducing data stored in capture buffer

1. A method of reducing an amount of data stored in a capture buffer of an interposer circuit during communication of the data over a data link according to a high-speed, layered packet-based protocol between a system under test and a protocol analyzer for analysis, without loss of functionality and without loss of available information for the analysis, the method comprising:

performing data integrity checks of the data in real time, and omitting data integrity bits corresponding to the data integrity checks from transaction layer packets (TLPs) and data link layer packets (DLLPs) of the data from being stored in the capture buffer when the data integrity checks indicate the data is correct;

performing acknowledge and negative acknowledge (ACK/NACK) matching in real time to indicate correct or incorrect arrival of the TLPs of the data using ACK/NACK packets, and omitting the ACK/NACK packets from being stored in the capture buffer; and

removing and/or reducing fields in real time from the TLPs and/or the DLLPs of the data to be stored in the capture buffer.

2. The method of claim 1 , further comprising:

compressing payloads of the TLPs and/or the DLLPs of the data in parallel to be stored in the capture buffer.

3. The method of claim 1 , wherein:

performing the data integrity checks of the data in real time comprises checking cyclic redundancy checkers (CRCs) in the TLPs and the DLLPs on the interposer circuit, and

omitting the data integrity bits from being stored comprises removing checksums of the CRCs that indicate no errors, wherein checksums of the CRCs that indicate errors are stored in the capture buffer.

4. The method of claim 3 , wherein:

performing the data integrity checks of the data in real time further comprises checking frame parity bits in the TLPs on the interposer circuit, and

omitting the data integrity bits from being stored further comprises omitting frame parity bits that indicate no errors, wherein frame parity bits that indicate errors are stored in the capture buffer.

5. The method of claim 1 , wherein the ACK/NACK packets are DLLPs, and

wherein, instead of storing the ACK/NACK DLLPs, the TLPs have meta data attached in the capture buffer respectively, wherein the meta data indicates an ACK/NACK status of the respective TLPs.

6. The method of claim 1 , wherein removing the fields from the TLPs and/or the DLLPs comprises one or more of:

removing known fields having fixed values and/or empty values, wherein the known fields are reinstated at a user interface;

removing framing tokens indicating starts and ends of packet flows of the TLPs and/or the DLLPs, wherein the framing tokens are replaced with smaller symbols or the framing tokens are removed; and

removing fields identified as non-required based on settings entered at the user interface.

7. The method of claim 1 , wherein reducing the fields from the TLPs comprises reducing a size of various address fields in the TLPs.

8. The method of claim 7 , further comprising implementing a lookup table for identifying active devices.

9. The method of claim 2 , wherein compressing payloads of the TLPs and/or the DLLPs of the data comprises:

receiving symbols from payloads of the TLPs and/or the DLLPs at the interposer circuit in a plurality of serial lanes

de-skewing the symbols from the payloads of the TLPs and/or the DLLPs into wide words arriving on each clock of a clock cycle;

arranging the wide words into input streams, wherein each input stream comprises symbols from the same position of each wide word arriving on each clock of the clock cycle;

compress the arranged and de-skewed symbols using a hash table; and

storing the compressed symbols in the capture buffer.

10. A system comprising:

a user interface (UI) computer configured to run analyzer software for analyzing data in a high-speed, layered packet-based protocol from a device under test (DUT) to a host computer via a high-speed data link according to the high-speed, layered packet-based protocol; and

an interposer circuit connected to the high-speed data link for monitoring the data transmitted between the DUT and the host computer, the interposer circuit comprising a capture buffer for storing the data transmitted between the DUT and the host computer, and accessible by the UI computer for analysis using the analyzer software, wherein the interposer circuit is programmed to:

perform data integrity checks of the data in real time, and omit data integrity bits corresponding to the data integrity checks from transaction layer packets (TLPs) and data link layer packets (DLLPs) of the data to be stored in the capture buffer when the data integrity checks indicate the data is correct;

perform acknowledge and negative acknowledge (ACK/NACK) matching in real time to indicate correct or incorrect arrival of the TLPs of the data using ACK/NACK packets, and omit the ACK/NACK packets from being stored in the capture buffer; and

remove and/or reduce fields in real time from the TLPs and/or the DLLPs of the data to be stored in the capture buffer.

11. The system of claim 10 , wherein the interposer circuit is programmed to:

perform the data integrity checks of the data in real time by checking cyclic redundancy checkers (CRCs) in the TLPs and the DLLPs on the interposer circuit, and

omit the data integrity bits from being stored by removing checksums of the CRCs that indicate no errors, wherein checksums of the CRCs that indicate errors are stored in the capture buffer.

12. The system of claim 11 , wherein the interposer circuit is programmed to:

perform the data integrity checks of the data in real time further by checking frame parity bits in the TLPs on the interposer circuit, and

omit the data integrity bits from being stored further by omitting frame parity bits that indicate no errors, wherein frame parity bits that indicate errors are stored in the capture buffer.

13. The system of claim 10 , wherein the ACK/NACK packets are DLLPs, and

wherein, instead of storing the ACK/NACK DLLPs, the TLPs have meta data attached in the capture buffer respectively, wherein the meta data indicates an ACK/NACK status of the respective TLPs.

14. The system of claim 10 , wherein the interposer circuit is programmed to remove the fields from the TLPs and/or the DLLPs by one or more of:

removing known fields having fixed values and/or empty values, wherein the known fields are reinstated at a user interface;

removing framing tokens indicating starts and ends of packet flows of the TLPs and/or the DLLPs, wherein the framing tokens are replaced with smaller symbols or the framing tokens are removed; and

removing fields identified as non-required based on settings entered at the user interface.

15. The system of claim 10 , wherein the interposer circuit is further programmed to:

compress payloads of the TLPs and/or the DLLPs of the data in parallel to be stored in the capture buffer.

16. The system of claim 15 , wherein the interposer circuit is programmed to compress the payloads of the TLPs and/or the DLLPs of the data in parallel by:

receiving symbols from payloads of the TLPs and/or the DLLPs at the interposer circuit in a plurality of serial lanes

de-skewing the symbols from the payloads of the TLPs and/or the DLLPs into wide words arriving on each clock of a clock cycle;

arranging the wide words into input streams, wherein each input stream comprises symbols from the same position of each wide word arriving on each clock of the clock cycle;

compress the arranged and de-skewed symbols using a hash table; and

storing the compressed symbols in the capture buffer.

17. The system of claim 16 , wherein the payloads of the TLPs and/or the DLLPs are compressed using one or more of LZW, LZ77 or LZ78 lossless data compression algorithms.

18. The system of claim 10 , wherein the interposer circuit comprises at least one of a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

19. A system comprising:

a user interface (UI) computer configured to run analyzer software for analyzing data in a high-speed, layered packet-based protocol from a device under test (DUT) to a host computer via a high-speed data link according to the high-speed, layered packet-based protocol; and

an interposer circuit connected to the high-speed data link for monitoring the data transmitted between the DUT and the host computer, the interposer circuit comprising a capture buffer for storing the data transmitted between the DUT and the host computer, and accessible by the UI computer for analysis using the analyzer software,

wherein the interposer circuit is programmed to compress in parallel transaction layer packets (TLPs) and/or data link layer packets (DLLPs), and to store the compressed TLPs and/or DLLPs in the capture buffer, wherein each of the TLPs and/or DLLPs comprises a header and a payload,

wherein compressing the TLPs and/or the DLLPs comprises:

receiving symbols of the TLPs and/or the DLLPs at the interposer circuit in a plurality of serial lanes;

de-skewing the symbols of the TLPs and/or the DLLPs into wide words arriving on each clock of a clock cycle;

arranging the wide words into input streams, wherein each input stream comprises symbols from the same position of each wide word arriving on each clock of the clock cycle; and

compressing the arranged symbols using a hash for storing in the capture buffer.

20. The system of claim 19 , wherein the hash table implements a hash function, as follows:

h ( j,x )=(( j>> 4){circumflex over ( )}( j<< 2){circumflex over ( )}( x<< 4))&“0xFFF”,

wherein “>>” means bitwise shift to the right, “<<” mean bitwise shift to the left, “{circumflex over ( )}” stands for a bitwise exclusive OR (XOR) logic operation, “&” stands for a bitwise AND logic operation, “j” is a reverse-pointer, and “x” is a character.