Methods and systems for software based prefetching for low buffer depth sequential read traffic

1. A method, comprising:

receiving, by a control circuitry while executing a storage device driver, at least one instruction of a stream of instructions for a storage device;

determining, by the control circuitry while executing the storage device driver, that a hardware buffer of the storage device is storing less than two instructions;

in response to determining that the hardware buffer of the storage device is storing less than two instructions:

accessing data associated with an address of a memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions; and

causing to be stored the data in a buffer, and

executing an instruction of the stream of instructions using at least the data stored in the buffer.

2. The method of claim 1 , the method further comprising:

receiving a sequential read command for reading data from the memory of the storage device, wherein:

the memory of the storage device comprises at least one floating gate NAND-based memory device, and

the at least one floating gate NAND-based memory device comprises at least two planes; and

without referencing a data cache, causing to be performed a read operation based on the sequential read command, wherein the read operation comprises a snap read across the at least two planes.

3. The method of claim 1 , wherein the hardware buffer of the storage device is storing exactly one instruction.

4. The method of claim 1 , wherein executing the instruction of the stream of instructions, by the control circuitry while executing the storage device driver, further comprises:

scheduling a prefetch command into the hardware buffer of the storage device.

5. The method of claim 1 , further comprising:

identifying, by the control circuitry while executing the storage device driver, the stream of instructions by detecting a particular number of sequential read instructions.

6. The method of claim 5 , further comprising:

configuring, by the control circuitry while executing the storage device driver, a plurality of buffers, wherein each buffer of the plurality of buffers is assigned a corresponding stream of instructions of a plurality of streams of instructions received by the driver of the storage device;

identifying a stale buffer among the plurality of buffers; and

marking the identified stale buffer to be reused.

7. The method of claim 6 , further comprising:

identifying a new stream;

determining that all buffers of the plurality of buffers are already assigned to streams of instructions; and

in response to identifying a new stream and determining that all buffers of the plurality of buffers are already assigned to streams of instructions:

determining a buffer of the plurality of buffers to be reused.

8. The method of claim 7 , wherein the determining a buffer of the plurality of buffers to be reused comprises:

determining a least recently used buffer of the plurality of buffers to be reused.

9. The method of claim 7 , wherein the determining a buffer of the plurality of buffers to be reused comprises:

determining a buffer of the plurality of buffers that is associated with a data address that is closest to a current data address of the at least one instruction of the stream of instructions.

10. The method of claim 1 , further comprising:

configuring, by the control circuitry while executing the storage device driver, a plurality of buffers;

identifying a new stream; and

assigning one of an unassigned buffer of the plurality of buffers to the new stream.

11. The method of claim 1 , further comprising:

configuring, by the control circuitry while executing the storage device driver, a plurality of buffers, wherein each buffer of the plurality of buffers is assigned a corresponding stream of instructions of a plurality of streams of instructions received by the storage device driver;

receiving a first read instruction as part of the stream of instructions for the storage device;

identifying a buffer of the plurality of buffers associated with the stream of instructions; and

accessing data associated with the address of the memory of the storage device, and

causing to be stored the data in the identified buffer of a plurality of buffers.

12. The method of claim 11 , further comprising:

determining that the identified buffer is full;

in response to determining that the identified buffer is full:

ceasing pre-fetching for the stream of instructions;

receiving an instruction as part of the stream of instructions for the storage device that hits a last storage location of the identified buffer;

in response to receiving an instruction as part of the stream of instructions for the storage device that hits the last storage location of the identified buffer:

resuming prefetching further data into the identified buffer.

13. The method of claim 11 , further comprising:

scheduling, by the control circuitry while executing the storage device driver, an additional access of second data from a second address of the storage device that is predicted by analyzing the at least one instruction of the stream of instructions.

14. The method of claim 13 , further comprising:

receiving, by the storage device driver, a second read instruction as part of the stream of instructions for the storage device; and

fulfilling the second read instruction by returning an accessed value stored in the identified buffer of the plurality of buffers.

15. A system, comprising:

a storage device; and

control circuitry, while executing a storage device driver of the storage device, to:

receive at least one instruction of a stream of instructions for the storage device;

determine that a hardware buffer of the storage device is storing less than two instructions;

in response to the determination that the hardware buffer of the storage device is storing less than two instructions:

access data associated with an address of a memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions, and

cause to be stored the data in a buffer of a plurality of buffers, and

execute an instruction of the stream of instructions using at least the data stored in the buffer.

16. The system of claim 15 , wherein the control circuitry further to:

receive a sequential read command for reading data from the memory of the storage device, wherein:

the memory of the storage device comprises at least one floating gate NAND-based memory device, and

the at least one floating gate NAND-based memory device comprises at least two planes; and

without referencing a data cache, causing to be performed a read operation based on the sequential read command, wherein the read operation comprises a snap read across the at least two planes.

17. The system of claim 15 , wherein the hardware buffer of the storage device is storing exactly one instruction.

18. The system of claim 15 , wherein to execute the instruction of the stream of instructions, the control circuitry is further to:

schedule a prefetch command into the hardware buffer of the storage device.

19. The system of claim 15 , wherein the control circuitry is further to:

identify the stream of instructions by detecting a particular number of sequential read instructions.

20. The system of claim 19 , wherein the control circuitry is further to:

configure a plurality of buffers, wherein each buffer of the plurality of buffers is assigned a corresponding stream of instructions of a plurality of streams of instructions received by the driver of the storage device;

identify a stale buffer among the plurality of buffers; and

mark the identified stale buffer to be reused.

21. The system of claim 20 , wherein the control circuitry is further to:

identify a new stream;

determine that all buffers of the plurality of buffers are already assigned to streams of instructions; and

in response to the identified new stream and the determination that all buffers of the plurality of buffers are already assigned to streams of instructions:

determine a buffer of the plurality of buffers to be reused.

22. The system of claim 21 , wherein to determine the buffer of the plurality of buffers, the control circuitry is to:

determine a least recently used buffer of the plurality of buffers to be reused.

23. The system of claim 22 , wherein the least recently used buffer of the plurality of buffers is a buffer that stores the oldest data to be accessed by the storage device driver.

24. A non-transitory computer-readable medium having non-transitory computer-readable instructions of a storage device driver encoded thereon that, when executed by a control circuitry, cause the control circuitry, while executing instructions of the storage device driver of a storage device, to:

receive at least one instruction of a stream of instructions for the storage device;

determine that a hardware buffer of the storage device is storing less than two instruction;

in response to the determination that the hardware buffer of the storage device is storing less than two instructions:

access data associated with an address of a memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions, and

cause to be stored the data in a buffer of a plurality of buffers, and execute an instruction of the stream of instructions using at least the data stored in the buffer.

25. The non-transitory computer-readable medium of claim 24 , wherein the control circuitry further to:

receive a sequential read command for reading data from the memory of the storage device, wherein:

the memory of the storage device comprises at least one floating gate NAND-based memory device, and

the at least one floating gate NAND-based memory device comprises at least two planes; and

without referencing a data cache, causing to be performed a read operation based on the sequential read command, wherein the read operation comprises a snap read across the at least two planes.

26. The non-transitory computer-readable medium of claim 24 , wherein the hardware buffer of the storage device is storing exactly one instruction.

27. The non-transitory computer-readable medium of claim 24 , wherein to execute the instruction of the stream of instructions, the control circuitry is further to:

schedule a prefetch command into the hardware buffer of the storage device.

28. The non-transitory computer-readable medium of claim 24 , wherein the control circuitry is further to:

identify the stream of instructions by detecting a particular number of sequential read instructions.

29. The non-transitory computer-readable medium of claim 28 ,

wherein the control circuitry is further to:

configure a plurality of buffers, wherein each buffer of the plurality of buffers is assigned a corresponding stream of instructions of a plurality of streams of instructions received by the driver of the storage device;

identify a stale buffer among the plurality of buffers; and

mark the identified stale buffer to be reused.

30. The non-transitory computer-readable medium of claim 29 ,

wherein the control circuitry is further to:

identify a new stream;

determine that all buffers of the plurality of buffers are already assigned to streams of instructions; and

in response to the identified new stream and the determination that all buffers of the plurality of buffers are already assigned to streams of instructions:

determine a buffer of the plurality of buffers to be reused.

31. The non-transitory computer-readable medium of claim 30 , wherein to determine the buffer of the plurality of buffers, the control circuitry is to:

determine a least recently used buffer of the plurality of buffers to be reused.

32. The non-transitory computer-readable medium of claim 31 , wherein the least recently used buffer of the plurality of buffers is a buffer that stores the oldest data to be accessed by the storage device driver.

33. The non-transitory computer-readable medium of claim 30 , wherein to determine the buffer of the plurality of buffers, the control circuitry is to:

determine a buffer of the plurality of buffers that is associated with a data address that is closest to a current data address of the one instruction of the stream of instructions.