IP Library Granted Patent US 12,568,828
Granted Patent B2
US 12,568,828 · App. 18/097,683 · Granted Mar 3, 2026

Method and system for fabricating regrown fiducials for semiconductor devices

Inventors: Karthik Suresh Arulalan (Santa Clara, CA); Jianfeng Wang (Santa Clara, CA); Sharlene Wilson (Santa Clara, CA); Mark Curtice (Santa Clara, CA); Subhash Srinivas Pidaparthi (Santa Clara, CA); Clifford Drowley (Santa Clara, CA)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/544H01L21/0254H01L21/0262H01L21/02639H01L21/02642H10D84/834H01L21/3065H01L21/3083H01L2223/54426H10D30/021H10D30/024H10D30/051
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Quick Facts
Patent No.
US 12,568,828
App. No.
18/097,683
Granted
Mar 3, 2026
Kind
B2
Abstract

A method of forming regrown fiducials includes providing a III-V compound substrate having a device region and an alignment mark region. The III-V compound substrate is characterized by a processing surface. The method also includes forming a hardmask layer having a first set of openings in the device region exposing a first surface portion of the processing surface of the III-V compound substrate and a second set of openings in the alignment mark region exposing a second surface portion of the processing surface and etching the first surface portion and the second surface portion of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches. The method also includes epitaxially regrowing a semiconductor layer in the trenches to form the regrown fiducials extending to a predetermined height over the processing surface in the alignment mark region.

Claims (17)

1 . A method of forming regrown fiducials, the method comprising:

providing a III-V compound substrate having a device region and an alignment mark region, wherein the III-V compound substrate is characterized by a processing surface;

forming a hardmask layer having a first set of openings in the device region exposing a first surface portion of the processing surface of the III-V compound substrate and a second set of openings in the alignment mark region exposing a second surface portion of the processing surface of the III-V compound substrate;

etching the first surface portion and the second surface portion of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches; and

epitaxially regrowing a semiconductor layer in the plurality of trenches to form the regrown fiducials extending to a predetermined height over the processing surface of the III-V compound substrate in the alignment mark region.

2 . The method of claim 1 wherein the III-V compound substrate comprises a GaN substrate and a plurality of epitaxial III-V layers.

3 . The method of claim 1 wherein the each of the plurality of trenches comprise a depth of about 0.8 μm.

4 . The method of claim 1 wherein the plurality of trenches in the device region each have a width of about 2 μm.

5 . The method of claim 1 wherein a width of the regrown fiducials is between 0.1 μm and 1 μm and a pitch of the regrown fiducials is between 0.2 μm and 1.2 μm.

6 . The method of claim 5 wherein the width is between 0.4 μm and 0.6 μm and the pitch is between 0.5 μm and 1.2 μm.

7 . The method of claim 1 wherein the plurality of trenches in the device region are characterized by a first pitch and the regrown fiducials are characterized by a second pitch less than the first pitch.

8 . The method of claim 1 wherein a set of regrown fiducials in the alignment mark region forms an alignment mark.

9 . The method of claim 1 wherein the regrown fiducials are elongated and a length of the regrown fiducials is parallel to an m-plane of the III-V compound substrate.

10 . The method of claim 1 wherein the first set of openings comprises an array of elongated openings arranged in parallel to each other configured to form a plurality of semiconductor fins.

11 . The method of claim 10 wherein the elongated openings each have a width in a range between about 0.2 μm and about 0.3 μm, a length in a range between about 10 μm and about 1000 μm, and a pitch between two adjacent elongated openings is in a range between about 1.9 μm and about 10 μm.

12 . The method of claim 1 wherein the III-V compound substrate comprises an n-GaN epitaxial layer and the semiconductor layer comprises a p-GaN epitaxial layer.

13 . The method of claim 1 wherein epitaxially regrowing the semiconductor layer is self-limiting in the alignment mark region.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 66783 FRAME: 161. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 24, 2024
From: NEXGEN (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 067217/0886 →
NUNC PRO TUNC ASSIGNMENT Recorded Apr 24, 2024
From: NEXGEN POWER SYSTEMS, INC.
To: NEXGEN (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 067852/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2024
From: NEXGEN POWER SYSTEMS, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 066783/0161 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2024
From: ARULALAN, KARTHIK SURESH; WANG, JIANFENG; WILSON, SHARLENE; CURTICE, MARK; PIDAPARTHI, SUBHASH SRINIVAS; DROWLEY, CLIFFORD
To: NEXGEN POWER SYSTEMS, INC.
Reel/Frame 066572/0350 →