Vertical fin-based field effect transistor (FinFET) with neutralized fin tips
A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of separated fins. Each of the separated fins has a length and a width measured laterally with respect to the length and includes a first fin tip disposed at a first end of the separated fin, a second fin tip disposed at a second end of the separated fin opposing the first end, a central region disposed between the first fin tip and the second fin tip and characterized by a first electrical conductivity, and a source contact electrically coupled to the central region. The first fin tip and the second fin tip are characterized by a second electrical conductivity less than the first electrical conductivity. The FinFET further includes a first gate region surrounding the first fin tip and a second gate region surrounding the second fin tip.
1 . A vertical fin-based field effect transistor (FinFET) device comprising:
an array of FinFETs comprising a plurality of rows and columns of separated fins, each of the separated fins having a fin length and a fin width measured laterally with respect to the fin length and including:
a first fin tip disposed at a first end of each of the separated fins;
a second fin tip disposed at a second end of each of the separated fins opposing the first end;
a central region disposed between the first fin tip and the second fin tip and characterized by a first electrical conductivity; and
a source contact electrically coupled to the central region, wherein the first fin tip and the second fin tip are characterized by a second electrical conductivity less than the first electrical conductivity;
a first gate region laterally adjacent the first fin tip; and
a second gate region laterally adjacent the second fin tip.
2 . The vertical FinFET device of claim 1 further comprising a first central gate region disposed on a first lateral side of each of the separated fins and a second central gate region disposed on a second lateral side of each of the separated fins, wherein the first central gate region and the second central gate region are characterized by a third electrical conductivity.
3 . The vertical FinFET device of claim 2 wherein the first gate region and the second gate region are characterized by a fourth electrical conductivity less than the third electrical conductivity.
4 . The vertical FinFET device of claim 1 wherein an area of the first fin tip is between 1% and 10% of an area of each of the separated fins and an area of the second fin tip is between 1% and 10% of an area of each of the separated fins.
5 . The vertical FinFET device of claim 1 wherein the separated fins comprise a III-N semiconductor.
6 . The vertical FinFET device of claim 1 wherein the first fin tip has a tip length and a ratio of the fin length to the tip length is greater than 10:1.
7 . The vertical FinFET device of claim 6 wherein the ratio is greater than 25:1.
8 . A method of fabricating a vertical fin-based field effect transistor (FinFET) device, the method comprising:
providing a III-N substrate structure;
forming a patterned hard mask coupled to the III-N substrate structure;
forming an array of separated fins in the III-N substrate structure, wherein each of the separated fins has a fin length and a fin width measured laterally with respect to the fin length;
forming a gate metal layer coupled to the III-N substrate structure;
forming a mask coupled to the III-N substrate structure;
electrically neutralizing:
a first fin tip disposed at a first end of each of the separated fins; and
a second fin tip disposed at a second end of each of the separated fins opposing the first end; and
forming a source contact electrically coupled to a central region of each of the separated fins, wherein the central region is disposed between the first fin tip and the second fin tip.
9 . The method of claim 8 wherein providing the III-N substrate structure comprises:
providing a III-nitride substrate;
epitaxially growing a first III-nitride layer coupled to the III-nitride substrate; and
epitaxially growing a second III-nitride layer coupled to the first III-nitride layer.
10 . The method of claim 9 wherein forming the patterned hard mask comprises:
forming a hard mask layer on the second III-nitride layer; and
patterning the hard mask layer to form the patterned hard mask.
11 . The method of claim 10 wherein forming the array of separated fins comprises:
etching the second III-nitride layer and a portion of the first III-nitride layer using the patterned hard mask to form a plurality of trenches; and
selectively regrowing a third III-nitride layer in the plurality of trenches.
12 . The method of claim 8 wherein:
the central region is characterized by a first electrical conductivity; and
the first fin tip and the second fin tip are characterized by a second electrical conductivity less than the first electrical conductivity.
13 . The method of claim 8 further comprising electrically neutralizing:
a first gate region laterally adjacent the first fin tip; and
a second gate region laterally adjacent the second fin tip.
14 . The method of claim 13 wherein electrically neutralizing the first gate region laterally adjacent the first fin tip and the second gate region laterally adjacent the second fin tip comprises performing implantation of ions.
15 . The method of claim 13 wherein forming the mask comprises:
providing a first mask portion that covers the central region of each of the separated fins,
providing a first opening in the mask that exposes the first fin tip and the first gate region; and
providing a second opening in the mask that exposes the second fin tip and the second gate region.
16 . The method of claim 8 wherein forming the gate metal layer coupled to the III-N substrate structure comprises:
forming a first central gate region disposed on a first lateral side of each of the separated fins; and
forming a second central gate region disposed on a second lateral side of each of the separated fins, wherein the first central gate region and the second central gate region are characterized by a third electrical conductivity.
17 . The method of claim 16 further comprising electrically neutralizing:
a first gate region laterally adjacent the first fin tip; and
a second gate region laterally adjacent the second fin tip,
wherein the first gate region and the second gate region are characterized by a fourth electrical conductivity less than the third electrical conductivity.
18 . The method of claim 8 wherein an area of the first fin tip is between 1% and 10% of an area of each of the separated fins, and an area of the second fin tip is between 1% and 10% of an area of each of the separated fins.
19 . The method of claim 8 wherein electrically neutralizing the first fin tip and the second fin tip comprises performing implantation of ions in the presence of the mask.
20 . The method of claim 8 wherein electrically neutralizing the first fin tip and the second fin tip comprises performing a hydrogen plasma treatment in the presence of the mask.